| Message ID | trinity-a908f45c-9600-475b-a182-f34055ffd4a6-1726430720847@3c-app-gmx-bap07 (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: tn40xx: add support for AQR105 based cards | expand |
diff --git a/drivers/net/ethernet/tehuti/tn40_mdio.c b/drivers/net/ethernet/tehuti/tn40_mdio.c index b8ee553f60d1..80eb68384389 100644 --- a/drivers/net/ethernet/tehuti/tn40_mdio.c +++ b/drivers/net/ethernet/tehuti/tn40_mdio.c @@ -185,6 +185,7 @@ int tn40_mdiobus_init(struct tn40_priv *priv) ret); } + tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_1MHZ); ret = devm_mdiobus_register(&pdev->dev, bus); if (ret) { dev_err(&pdev->dev, "failed to register mdiobus %d %u %u\n",
Prepare the tn40xx driver to load for Tehuti TN9510 cards, which require bit 3 in the register TN40_REG_MDIO_CMD_STAT to be set. The function of bit 3 is unclear, but may have something to do with the length of the preamble in the MDIO communication. If bit 3 is not set, the PHY will not be found when performing a scan for PHYs. Use the available tn40_mdio_set_speed funtion which includes setting bit 3. Signed-off-by: Hans-Frieder Vogt <hfdevel@gmx.net> --- drivers/net/ethernet/tehuti/tn40_mdio.c | 1 + 1 file changed, 1 insertion(+) -- 2.45.2