diff mbox

[OPW,kernel] staging/cxt1e1:Fixes incorrect brace placement

Message ID 20131030184949.GA24215@dshgna
State New, archived
Headers show

Commit Message

Dulshani Gunawardhana Oct. 30, 2013, 6:49 p.m. UTC
This patch fixes the error "This open brace { should be on the
above line" detected via checkpatch.pl.

Signed-off-by: Dulshani Gunawardhana <dulshani.gunawardhana89@gmail.com>
Reviewed-by: Zach Brown <zab@redhat.com>
---
 drivers/staging/cxt1e1/comet.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

Comments

Josh Triplett Nov. 3, 2013, 6:18 p.m. UTC | #1
On Thu, Oct 31, 2013 at 12:19:54AM +0530, Dulshani Gunawardhana wrote:
> This patch fixes the error "This open brace { should be on the
> above line" detected via checkpatch.pl.
> 
> Signed-off-by: Dulshani Gunawardhana <dulshani.gunawardhana89@gmail.com>
> Reviewed-by: Zach Brown <zab@redhat.com>

Reviewed-by: Josh Triplett <josh@joshtriplett.org>

>  drivers/staging/cxt1e1/comet.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
> index 46a0d92..6b3182a 100644
> --- a/drivers/staging/cxt1e1/comet.c
> +++ b/drivers/staging/cxt1e1/comet.c
> @@ -159,8 +159,7 @@ void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
>      /* 60: t1 ALMI cfg */
>      /* Configure Line Coding */
>  
> -	switch (port_mode)
> -	{
> +	switch (port_mode) {
>  	/* 1 - T1 B8ZS */
>  	case CFG_FRAME_SF:
>  		pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
> @@ -286,8 +285,7 @@ void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
>  
>      /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
>      /* note "rate bits can only be set once after reset" */
> -	if (clockmaster)
> -		{
> +	if (clockmaster) {
>  		/* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
>  		/* rate = 1.544 Mb/s */
>  		if (isT1mode)
> @@ -302,8 +300,7 @@ void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
>  
>  		/* Master Mode i.e.FPMODE=0 (@0x20) */
>  		pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
> -		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
> -			{
> +		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
>  			if (cxt1e1_log_level >= LOG_SBEBUG12)
>  				pr_info(">> %s: clockmaster internal clock\n", __func__);
>  			/* internal oscillator */
> @@ -422,8 +419,7 @@ WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
>  {
>  	u_int32_t sample, unit;
>  
> -	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
> -		{
> +	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
>  		for (unit = 0; unit < COMET_NUM_UNITS; unit++)
>  			WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
>  		}
> @@ -554,8 +550,7 @@ SetCometOps(comet_t *comet)
>  {
>  	volatile u_int8_t rd_value;
>  
> -	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
> -	{
> +	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
>  		/* read the BRIF Configuration */
>  		rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
>  		rd_value &= ~0x20;
> -- 
> 1.8.1.2
> 
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'Greg KH' Nov. 10, 2013, 4 p.m. UTC | #2
On Thu, Oct 31, 2013 at 12:19:54AM +0530, Dulshani Gunawardhana wrote:
> This patch fixes the error "This open brace { should be on the
> above line" detected via checkpatch.pl.
> 
> Signed-off-by: Dulshani Gunawardhana <dulshani.gunawardhana89@gmail.com>
> Reviewed-by: Zach Brown <zab@redhat.com>
> Reviewed-by: Josh Triplett <josh@joshtriplett.org>

Applied, thanks.

greg k-h
diff mbox

Patch

diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
index 46a0d92..6b3182a 100644
--- a/drivers/staging/cxt1e1/comet.c
+++ b/drivers/staging/cxt1e1/comet.c
@@ -159,8 +159,7 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
     /* 60: t1 ALMI cfg */
     /* Configure Line Coding */
 
-	switch (port_mode)
-	{
+	switch (port_mode) {
 	/* 1 - T1 B8ZS */
 	case CFG_FRAME_SF:
 		pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
@@ -286,8 +285,7 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 
     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
     /* note "rate bits can only be set once after reset" */
-	if (clockmaster)
-		{
+	if (clockmaster) {
 		/* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
 		/* rate = 1.544 Mb/s */
 		if (isT1mode)
@@ -302,8 +300,7 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 
 		/* Master Mode i.e.FPMODE=0 (@0x20) */
 		pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
-		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
-			{
+		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
 			if (cxt1e1_log_level >= LOG_SBEBUG12)
 				pr_info(">> %s: clockmaster internal clock\n", __func__);
 			/* internal oscillator */
@@ -422,8 +419,7 @@  WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
 {
 	u_int32_t sample, unit;
 
-	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
-		{
+	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
 		for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 			WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
 		}
@@ -554,8 +550,7 @@  SetCometOps(comet_t *comet)
 {
 	volatile u_int8_t rd_value;
 
-	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
-	{
+	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
 		/* read the BRIF Configuration */
 		rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 		rd_value &= ~0x20;