From patchwork Tue Nov 12 04:06:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 11238529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D4741515 for ; Tue, 12 Nov 2019 04:06:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 041FA20840 for ; Tue, 12 Nov 2019 04:06:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726939AbfKLEGn (ORCPT ); Mon, 11 Nov 2019 23:06:43 -0500 Received: from mga14.intel.com ([192.55.52.115]:34570 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726927AbfKLEGn (ORCPT ); Mon, 11 Nov 2019 23:06:43 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Nov 2019 20:06:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,295,1569308400"; d="scan'208";a="202576628" Received: from unknown (HELO gayuk-dev-mach.sc.intel.com) ([10.3.79.161]) by fmsmga007.fm.intel.com with ESMTP; 11 Nov 2019 20:06:42 -0800 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: vishwanath.somayaji@intel.com, dvhart@infradead.org, linux-kernel@vger.kernel.org, charles.d.prestopine@intel.com, Gayatri Kammela , Peter Zijlstra , Srinivas Pandruvada , Andy Shevchenko , Kan Liang , "David E . Box" , Rajneesh Bhardwaj , Tony Luck Subject: [PATCH v2 0/6] x86/intel_pmc_core: Add Tiger Lake and Elkhart Lake Date: Mon, 11 Nov 2019 20:06:25 -0800 Message-Id: X-Mailer: git-send-email 2.17.1 Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Hi, Patch 1: Fix SoC naming inconsistency Patch 2: Cleans up termination lines Patch 3: Refactor driver for ease of adding new SoCs Patch 4: Add debugfs entry for PCH IPs only if platform supports Patch 5: Add Tiger Lake legacy support to pmc_core Patch 6: Add Elkhart Lake legacy support to pmc_core All the information regarding the PCH IPs and names of IPs will be available in Intel's Platform Controller Hub (PCH) External Design Specification (EDS) document expected to be released in 2020 before product launch. Changes since v1: 1)Added a patch that fixes the naming inconsistency. 2)Fixed the prefix of all the patches. Gayatri Kammela (6): x86/intel_pmc_core: Fix the SoC naming inconsistency x86/intel_pmc_core: Clean up: Remove comma after the termination line x86/intel_pmc_core: Create platform dependent pmc bitmap structs x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status conditional platform/x86: Add Tiger Lake (TGL) platform support to intel_pmc_core driver platform/x86: Add Atom based Elkhart Lake (EHL) platform support to intel_pmc_core driver drivers/platform/x86/intel_pmc_core.c | 118 ++++++++++++++++++++------ drivers/platform/x86/intel_pmc_core.h | 2 +- 2 files changed, 93 insertions(+), 27 deletions(-) Cc: Peter Zijlstra Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck