From patchwork Thu Dec 12 18:38:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 11289133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B9E9109A for ; Thu, 12 Dec 2019 18:40:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54017206DA for ; Thu, 12 Dec 2019 18:40:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730422AbfLLSkm (ORCPT ); Thu, 12 Dec 2019 13:40:42 -0500 Received: from mga01.intel.com ([192.55.52.88]:22235 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730393AbfLLSkm (ORCPT ); Thu, 12 Dec 2019 13:40:42 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Dec 2019 10:40:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,306,1571727600"; d="scan'208";a="211205403" Received: from gayuk-dev-mach.sc.intel.com ([10.3.79.172]) by fmsmga008.fm.intel.com with ESMTP; 12 Dec 2019 10:40:42 -0800 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: vishwanath.somayaji@intel.com, dvhart@infradead.org, linux-kernel@vger.kernel.org, mika.westerberg@intel.com, charles.d.prestopine@intel.com, Gayatri Kammela , Peter Zijlstra , Srinivas Pandruvada , Andy Shevchenko , Kan Liang , "David E . Box" , Rajneesh Bhardwaj , Tony Luck Subject: [PATCH v4 0/5] platform/x86: intel_pmc_core: Add Tiger Lake and Date: Thu, 12 Dec 2019 10:38:42 -0800 Message-Id: X-Mailer: git-send-email 2.17.1 Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Hi, Patch 1: Cleans up termination lines Patch 2: Refactor driver for ease of adding new SoCs Patch 3: Add debugfs entry for PCH IPs only if platform supports Patch 4: Add Tiger Lake legacy support to pmc_core Patch 5: Add Elkhart Lake legacy support to pmc_core All the information regarding the PCH IPs and names of IPs will be available in Intel's Platform Controller Hub (PCH) External Design Specification (EDS) document expected to be released in 2020 before product launch. Changes since v1: 1) Added a patch that fixes the naming inconsistency. 2) Fixed the prefix of all the patches. Changes since v2: 1) Add Comet Lake legacy support to pmc_core up on Dell's request. Changes since v3: 1) Removed both "SoC naming inconsistency" patch and "Add Comet Lake legacy support to pmc_core" patch from this series and sent them as a series which was made upstream. 2) Updated LTR IGNORE Max offset for Tiger Lake and Elkhart Lake by defining a macro as they are platform specific. Gayatri Kammela (5): platform/x86: intel_pmc_core: Clean up: Remove comma after the termination line platform/x86: intel_pmc_core: Create platform dependent pmc bitmap structs platform/x86: intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status conditional platform/x86: intel_pmc_core: Add Tiger Lake (TGL) platform support to intel_pmc_core driver platform/x86: intel_pmc_core: Add Atom based Elkhart Lake (EHL) platform support to intel_pmc_core driver drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++----- drivers/platform/x86/intel_pmc_core.h | 4 +- 2 files changed, 90 insertions(+), 22 deletions(-) Cc: Peter Zijlstra Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck