From patchwork Thu Dec 7 01:54:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Sakkinen X-Patchwork-Id: 10097523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D463960327 for ; Thu, 7 Dec 2017 01:57:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C399529D85 for ; Thu, 7 Dec 2017 01:57:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B732529DF0; Thu, 7 Dec 2017 01:57:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40A7929D85 for ; Thu, 7 Dec 2017 01:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752506AbdLGB5c (ORCPT ); Wed, 6 Dec 2017 20:57:32 -0500 Received: from mga07.intel.com ([134.134.136.100]:56312 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752500AbdLGB5b (ORCPT ); Wed, 6 Dec 2017 20:57:31 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Dec 2017 17:57:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,370,1508828400"; d="scan'208";a="156691401" Received: from dsdeshpa-mobl2.gar.corp.intel.com (HELO localhost) ([10.249.254.89]) by orsmga004.jf.intel.com with ESMTP; 06 Dec 2017 17:57:23 -0800 From: Jarkko Sakkinen To: intel-sgx-kernel-dev@lists.01.org, platform-driver-x86@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Haim Cohen , Jarkko Sakkinen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Len Brown , Kyle Huey , Borislav Petkov , Tom Lendacky , Grzegorz Andrejczuk Subject: [PATCH v7 3/8] x86: add SGX definitions to msr-index.h Date: Thu, 7 Dec 2017 03:54:03 +0200 Message-Id: <20171207015614.7914-4-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171207015614.7914-1-jarkko.sakkinen@linux.intel.com> References: <20171207015614.7914-1-jarkko.sakkinen@linux.intel.com> Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Christopherson ENCLS and ENCLU are usable if and only if SGX_ENABLE is set and After SGX is activated the IA32_SGXLEPUBKEYHASHn MSRs are writable if SGX_LC_WR is set and the feature control is locked. SGX related bits in IA32_FEATURE_CONTROL cannot be set before SGX is activated by the pre-boot firmware. SGX activation is triggered by setting bit 0 in the MSR 0x7a. Until SGX is activated, the LE hash MSRs are writable to allow pre-boot firmware to lock down the LE root key with a non-Intel value. Signed-off-by: Sean Christopherson Signed-off-by: Haim Cohen Signed-off-by: Jarkko Sakkinen --- arch/x86/include/asm/msr-index.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 34c4922bbc3f..8647a2470487 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -439,6 +439,8 @@ #define FEATURE_CONTROL_LOCKED (1<<0) #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) +#define FEATURE_CONTROL_SGX_ENABLE (1<<18) +#define FEATURE_CONTROL_SGX_LE_WR (1<<17) #define FEATURE_CONTROL_LMCE (1<<20) #define MSR_IA32_APICBASE 0x0000001b @@ -505,6 +507,12 @@ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +/* Intel SGX MSRs */ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F + /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) #define THERM_SHIFT_THRESHOLD0 8