| Message ID | 20180216104751.8371-9-hdegoede@redhat.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Andy Shevchenko |
| Headers | show |
On Fri, Feb 16, 2018 at 11:47:47AM +0100, Hans de Goede wrote: > The xHCI controller on various Intel SoCs has an extended cap mmio-range > which contains registers to control the muxing to the xHCI (host mode) > or the dwc3 (device mode) and vbus-detection for the otg usb-phy. > > Having a role-sw driver included in the xhci code (under drivers/usb/host) > is not desirable. So this commit adds a simple handler for this extended > capability, which creates a platform device with the caps mmio region as > resource, this allows us to write a separate platform role-sw driver for > the role-switch. > > Note this commit adds a call to the new xhci_ext_cap_init() function > to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must > be called only once. If in the future we also want to handle ext-caps > on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also > be added to other bus probe paths. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Thanks,
On Fri, Feb 16, 2018 at 12:47 PM, Hans de Goede <hdegoede@redhat.com> wrote: > The xHCI controller on various Intel SoCs has an extended cap mmio-range > which contains registers to control the muxing to the xHCI (host mode) > or the dwc3 (device mode) and vbus-detection for the otg usb-phy. > > Having a role-sw driver included in the xhci code (under drivers/usb/host) > is not desirable. So this commit adds a simple handler for this extended > capability, which creates a platform device with the caps mmio region as > resource, this allows us to write a separate platform role-sw driver for > the role-switch. > > Note this commit adds a call to the new xhci_ext_cap_init() function > to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must > be called only once. If in the future we also want to handle ext-caps > on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also > be added to other bus probe paths. SPDX? > +/* > + * XHCI extended capability handling > + * > + * Copyright (c) 2017 Hans de Goede <hdegoede@redhat.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + pdev = platform_device_alloc("intel_xhci_usb_sw", PLATFORM_DEVID_NONE); Perhaps, #define USB_SW_DRV_NAME "..." > + if (!pdev) { > + xhci_err(xhci, "couldn't allocate intel_xhci_usb_sw pdev\n"); ...and re-use it everywhere here. pdev -> platform device. > + return -ENOMEM; > + } > + > + res.start = hcd->rsrc_start + cap_offset; > + res.end = res.start + 0x3ff; Is this magic always the same? Where its value comes from? At least define with comment. > +int xhci_ext_cap_init(struct xhci_hcd *xhci) > +{ > + void __iomem *base = &xhci->cap_regs->hc_capbase; > + u32 cap_offset, val; > + int ret; > + > + cap_offset = xhci_find_next_ext_cap(base, 0, 0); > + > + while (cap_offset) { > + val = readl(base + cap_offset); > + > + switch (XHCI_EXT_CAPS_ID(val)) { > + case XHCI_EXT_CAPS_VENDOR_INTEL: > + if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { > + ret = xhci_create_intel_xhci_sw_pdev( > + xhci, cap_offset); Can we leave xhci on previous line? > + if (ret) > + return ret; > + } > + break; > + } > + cap_offset = xhci_find_next_ext_cap(base, cap_offset, 0); > + } > + > + return 0; > +}
Hi, On 16-02-18 14:53, Andy Shevchenko wrote: > On Fri, Feb 16, 2018 at 12:47 PM, Hans de Goede <hdegoede@redhat.com> wrote: >> The xHCI controller on various Intel SoCs has an extended cap mmio-range >> which contains registers to control the muxing to the xHCI (host mode) >> or the dwc3 (device mode) and vbus-detection for the otg usb-phy. >> >> Having a role-sw driver included in the xhci code (under drivers/usb/host) >> is not desirable. So this commit adds a simple handler for this extended >> capability, which creates a platform device with the caps mmio region as >> resource, this allows us to write a separate platform role-sw driver for >> the role-switch. >> >> Note this commit adds a call to the new xhci_ext_cap_init() function >> to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must >> be called only once. If in the future we also want to handle ext-caps >> on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also >> be added to other bus probe paths. > > SPDX? Ack, fixed for v2. >> +/* >> + * XHCI extended capability handling >> + * >> + * Copyright (c) 2017 Hans de Goede <hdegoede@redhat.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ > >> + pdev = platform_device_alloc("intel_xhci_usb_sw", PLATFORM_DEVID_NONE); > > Perhaps, > > #define USB_SW_DRV_NAME "..." Ack, fixed for v2. >> + if (!pdev) { >> + xhci_err(xhci, "couldn't allocate intel_xhci_usb_sw pdev\n"); > > ...and re-use it everywhere here. > > pdev -> platform device. > >> + return -ENOMEM; >> + } >> + >> + res.start = hcd->rsrc_start + cap_offset; >> + res.end = res.start + 0x3ff; > > Is this magic always the same? Where its value comes from? > At least define with comment. Ack, I've added a USB_SW_RESOURCE_SIZE #define for this for v2. >> +int xhci_ext_cap_init(struct xhci_hcd *xhci) >> +{ >> + void __iomem *base = &xhci->cap_regs->hc_capbase; >> + u32 cap_offset, val; >> + int ret; >> + >> + cap_offset = xhci_find_next_ext_cap(base, 0, 0); >> + >> + while (cap_offset) { >> + val = readl(base + cap_offset); >> + >> + switch (XHCI_EXT_CAPS_ID(val)) { >> + case XHCI_EXT_CAPS_VENDOR_INTEL: >> + if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { > >> + ret = xhci_create_intel_xhci_sw_pdev( >> + xhci, cap_offset); > > Can we leave xhci on previous line? Fixed for v2. >> + if (ret) >> + return ret; >> + } >> + break; >> + } >> + cap_offset = xhci_find_next_ext_cap(base, cap_offset, 0); >> + } >> + >> + return 0; >> +} > > Regards, Hans
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 4ede4ce12366..8a8cffe0b445 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -11,7 +11,7 @@ fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o -xhci-hcd-y := xhci.o xhci-mem.o +xhci-hcd-y := xhci.o xhci-mem.o xhci-ext-caps.o xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o xhci-hcd-y += xhci-trace.o diff --git a/drivers/usb/host/xhci-ext-caps.c b/drivers/usb/host/xhci-ext-caps.c new file mode 100644 index 000000000000..8622d1e95ae7 --- /dev/null +++ b/drivers/usb/host/xhci-ext-caps.c @@ -0,0 +1,89 @@ +/* + * XHCI extended capability handling + * + * Copyright (c) 2017 Hans de Goede <hdegoede@redhat.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include "xhci.h" + +static void xhci_intel_unregister_pdev(void *arg) +{ + platform_device_unregister(arg); +} + +static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset) +{ + struct usb_hcd *hcd = xhci_to_hcd(xhci); + struct device *dev = hcd->self.controller; + struct platform_device *pdev; + struct resource res = { 0, }; + int ret; + + pdev = platform_device_alloc("intel_xhci_usb_sw", PLATFORM_DEVID_NONE); + if (!pdev) { + xhci_err(xhci, "couldn't allocate intel_xhci_usb_sw pdev\n"); + return -ENOMEM; + } + + res.start = hcd->rsrc_start + cap_offset; + res.end = res.start + 0x3ff; + res.name = "intel_xhci_usb_sw"; + res.flags = IORESOURCE_MEM; + + ret = platform_device_add_resources(pdev, &res, 1); + if (ret) { + dev_err(dev, "couldn't add resources to intel_xhci_usb_sw pdev\n"); + platform_device_put(pdev); + return ret; + } + + pdev->dev.parent = dev; + + ret = platform_device_add(pdev); + if (ret) { + dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n"); + platform_device_put(pdev); + return ret; + } + + ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev); + if (ret) { + dev_err(dev, "couldn't add unregister action for intel_xhci_usb_sw pdev\n"); + return ret; + } + + return 0; +} + +int xhci_ext_cap_init(struct xhci_hcd *xhci) +{ + void __iomem *base = &xhci->cap_regs->hc_capbase; + u32 cap_offset, val; + int ret; + + cap_offset = xhci_find_next_ext_cap(base, 0, 0); + + while (cap_offset) { + val = readl(base + cap_offset); + + switch (XHCI_EXT_CAPS_ID(val)) { + case XHCI_EXT_CAPS_VENDOR_INTEL: + if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { + ret = xhci_create_intel_xhci_sw_pdev( + xhci, cap_offset); + if (ret) + return ret; + } + break; + } + cap_offset = xhci_find_next_ext_cap(base, cap_offset, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(xhci_ext_cap_init); diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h index 631e7cc62604..268328c20681 100644 --- a/drivers/usb/host/xhci-ext-caps.h +++ b/drivers/usb/host/xhci-ext-caps.h @@ -39,6 +39,8 @@ #define XHCI_EXT_CAPS_ROUTE 5 /* IDs 6-9 reserved */ #define XHCI_EXT_CAPS_DEBUG 10 +/* Vendor caps */ +#define XHCI_EXT_CAPS_VENDOR_INTEL 192 /* USB Legacy Support Capability - section 7.1.1 */ #define XHCI_HC_BIOS_OWNED (1 << 16) #define XHCI_HC_OS_OWNED (1 << 24) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 6c79037876db..4486640d925c 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -164,6 +164,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { xhci->quirks |= XHCI_SSIC_PORT_UNUSED; + xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; } if (pdev->vendor == PCI_VENDOR_ID_INTEL && (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || @@ -297,6 +298,10 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) goto dealloc_usb2_hcd; } + retval = xhci_ext_cap_init(xhci); + if (retval) + goto put_usb3_hcd; + retval = usb_add_hcd(xhci->shared_hcd, dev->irq, IRQF_SHARED); if (retval) diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 96099a245c69..5917e3095e2a 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1825,6 +1825,7 @@ struct xhci_hcd { /* Reserved. It was XHCI_U2_DISABLE_WAKE */ #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) #define XHCI_HW_LPM_DISABLE (1 << 29) +#define XHCI_INTEL_USB_ROLE_SW (1 << 30) unsigned int num_active_eps; unsigned int limit_active_eps; @@ -2020,6 +2021,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); void xhci_init_driver(struct hc_driver *drv, const struct xhci_driver_overrides *over); int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); +int xhci_ext_cap_init(struct xhci_hcd *xhci); int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); int xhci_resume(struct xhci_hcd *xhci, bool hibernated);