From patchwork Wed Nov 20 00:22:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: srinivas pandruvada X-Patchwork-Id: 11252907 X-Patchwork-Delegate: andy.shevchenko@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2EBA014C0 for ; Wed, 20 Nov 2019 00:23:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 16804222B0 for ; Wed, 20 Nov 2019 00:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727222AbfKTAXA (ORCPT ); Tue, 19 Nov 2019 19:23:00 -0500 Received: from mga17.intel.com ([192.55.52.151]:31037 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727202AbfKTAXA (ORCPT ); Tue, 19 Nov 2019 19:23:00 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Nov 2019 16:23:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,219,1571727600"; d="scan'208";a="204562371" Received: from spandruv-mobl.jf.intel.com ([10.254.110.151]) by fmsmga008.fm.intel.com with ESMTP; 19 Nov 2019 16:22:59 -0800 From: Srinivas Pandruvada To: andriy.shevchenko@intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, prarit@redhat.com, Srinivas Pandruvada Subject: [PATCH] tools/power/x86/intel-speed-select: Display TRL buckets for just base config level Date: Tue, 19 Nov 2019 16:22:54 -0800 Message-Id: <20191120002254.13842-1-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.17.2 Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org When only base config level is present, this tool is displaying TRL (Turbo-ratio-limits) by reading legacy MSR. In this case, also present core count for TRL by reading MSR 0x1AE. Signed-off-by: Srinivas Pandruvada --- tools/power/x86/intel-speed-select/isst-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index aa19c9998e6c..d14c7bcd327a 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) } isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores); + isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info); continue; }