From patchwork Thu Dec 16 02:31:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12679881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52DAAC433EF for ; Thu, 16 Dec 2021 02:32:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232973AbhLPCbt (ORCPT ); Wed, 15 Dec 2021 21:31:49 -0500 Received: from mga06.intel.com ([134.134.136.31]:23292 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229980AbhLPCbs (ORCPT ); Wed, 15 Dec 2021 21:31:48 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10199"; a="300162497" X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="300162497" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2021 18:31:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="545805656" Received: from linux.intel.com ([10.54.29.200]) by orsmga001.jf.intel.com with ESMTP; 15 Dec 2021 18:31:47 -0800 Received: from debox1-desk4.intel.com (unknown [10.209.86.221]) by linux.intel.com (Postfix) with ESMTP id 3C703580D6F; Wed, 15 Dec 2021 18:31:47 -0800 (PST) From: "David E. Box" To: lee.jones@linaro.org, hdegoede@redhat.com, david.e.box@linux.intel.com, bhelgaas@google.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, srinivas.pandruvada@intel.com, mgross@linux.intel.com Cc: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org, "Rafael J . Wysocki" Subject: [PATCH V4 1/6] PCI: Add #defines for accessing PCIe DVSEC fields Date: Wed, 15 Dec 2021 18:31:41 -0800 Message-Id: <20211216023146.2361174-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216023146.2361174-1-david.e.box@linux.intel.com> References: <20211216023146.2361174-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Add #defines for accessing Vendor ID, Revision, Length, and ID offsets in the Designated Vendor Specific Extended Capability (DVSEC). Defined in PCIe r5.0, sec 7.9.6. Signed-off-by: David E. Box Acked-by: Bjorn Helgaas Reviewed-by: Rafael J. Wysocki --- V4 - No changes V3 - No changes V2 - No changes include/uapi/linux/pci_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ff6ccbc6efe9..318f3f1f9e92 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1086,7 +1086,11 @@ /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ +#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff) +#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf) +#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff) #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ +#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff) /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */