| Message ID | 20220128171804.569796-11-brijesh.singh@amd.com (mailing list archive) |
|---|---|
| State | Deferred, archived |
| Headers | show |
| Series | Add AMD Secure Nested Paging (SEV-SNP) Guest Support | expand |
On Fri, Jan 28, 2022 at 11:17:31AM -0600, Brijesh Singh wrote: > diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c > index 9b93567d663a..63e9044ab1d6 100644 > --- a/arch/x86/boot/compressed/idt_64.c > +++ b/arch/x86/boot/compressed/idt_64.c > @@ -39,7 +39,15 @@ void load_stage1_idt(void) > load_boot_idt(&boot_idt_desc); > } > > -/* Setup IDT after kernel jumping to .Lrelocated */ > +/* > + * Setup IDT after kernel jumping to .Lrelocated > + * > + * initialize_identity_maps() needs a PF handler setup. The PF handler setup > + * needs to happen in load_stage2_idt() where the IDT is loaded and there the > + * VC IDT entry gets setup too in order to handle VCs, one needs a GHCB which > + * gets setup with an already setup table which is done in > + * initialize_identity_maps() and this is where the circle is complete. > + */ I've beefed it up more, please use this one instead: /* * Setup IDT after kernel jumping to .Lrelocated. * * initialize_identity_maps() needs a #PF handler to be setup * in order to be able to fault-in identity mapping ranges; see * do_boot_page_fault(). * * This #PF handler setup needs to happen in load_stage2_idt() where the * IDT is loaded and there the #VC IDT entry gets setup too. * * In order to be able to handle #VCs, one needs a GHCB which * gets setup with an already set up pagetable, which is done in * initialize_identity_maps(). And there's the catch 22: the boot #VC * handler do_boot_stage2_vc() needs to call early_setup_ghcb() itself * (and, especially set_page_decrypted()) because the SEV-ES setup code * cannot initialize a GHCB as there's no #PF handler yet... */ > diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c > index 19ad09712902..24df739c9c05 100644 > --- a/arch/x86/kernel/sev.c > +++ b/arch/x86/kernel/sev.c > @@ -43,6 +43,9 @@ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); > */ > static struct ghcb __initdata *boot_ghcb; > > +/* Bitmap of SEV features supported by the hypervisor */ > +static u64 sev_hv_features __ro_after_init; > + > /* #VC handler runtime per-CPU data */ > struct sev_es_runtime_data { > struct ghcb ghcb_page; > @@ -766,6 +769,18 @@ void __init sev_es_init_vc_handling(void) > if (!sev_es_check_cpu_features()) > panic("SEV-ES CPU Features missing"); > > + /* > + * SEV-SNP is supported in v2 of the GHCB spec which mandates support for HV > + * features. If SEV-SNP is enabled, then check if the hypervisor supports > + * the SEV-SNP features. You guys have been completely brainwashed by marketing. I say: "s/SEV-SNP/SNP/g And please do that everywhere in sev-specific files." and you go and slap that "SEV-" thing everywhere instead. Why? That file is already called sev.c so it must be SEV-something. Lemme simplify that comment for ya: /* * SNP is supported in v2 of the GHCB spec which mandates support for HV * features. */ That's it, no more needed - the rest should be visible from the code. Thx.
On 2/1/22 1:59 PM, Borislav Petkov wrote: ... > >> diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c >> index 19ad09712902..24df739c9c05 100644 >> --- a/arch/x86/kernel/sev.c >> +++ b/arch/x86/kernel/sev.c >> @@ -43,6 +43,9 @@ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); >> */ >> static struct ghcb __initdata *boot_ghcb; >> >> +/* Bitmap of SEV features supported by the hypervisor */ >> +static u64 sev_hv_features __ro_after_init; >> + >> /* #VC handler runtime per-CPU data */ >> struct sev_es_runtime_data { >> struct ghcb ghcb_page; >> @@ -766,6 +769,18 @@ void __init sev_es_init_vc_handling(void) >> if (!sev_es_check_cpu_features()) >> panic("SEV-ES CPU Features missing"); >> >> + /* >> + * SEV-SNP is supported in v2 of the GHCB spec which mandates support for HV >> + * features. If SEV-SNP is enabled, then check if the hypervisor supports >> + * the SEV-SNP features. > > You guys have been completely brainwashed by marketing. I say: > > "s/SEV-SNP/SNP/g > > And please do that everywhere in sev-specific files." Yeah, most of the documentation explicitly calls SEV-SNP, I was unsure about the trademark, so I used it in the comments/logs. I am okay with the SEV prefix removed; I am not in the marketing team, and hopefully, they will *never* see kernel code ;) ~ Brijesh
On Wed, Feb 02, 2022 at 08:28:17AM -0600, Brijesh Singh wrote: > Yeah, most of the documentation explicitly calls SEV-SNP, I was unsure about > the trademark, so I used it in the comments/logs. I am okay with the SEV > prefix removed; I am not in the marketing team, and hopefully, they will > *never* see kernel code ;) They better! :-) Also, in our kernel team here, the importance lies on having stuff clearly and succinctly explained, without any bla or fluff. When you look at that code later, you should go "ah, ok, that's why we're doing this here" - not, "uuh, I need to sit down and parse that comment first." That's why I'd like for comments to have only good and important words - no deadweight marketing bla. :-)
diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c index 9b93567d663a..63e9044ab1d6 100644 --- a/arch/x86/boot/compressed/idt_64.c +++ b/arch/x86/boot/compressed/idt_64.c @@ -39,7 +39,15 @@ void load_stage1_idt(void) load_boot_idt(&boot_idt_desc); } -/* Setup IDT after kernel jumping to .Lrelocated */ +/* + * Setup IDT after kernel jumping to .Lrelocated + * + * initialize_identity_maps() needs a PF handler setup. The PF handler setup + * needs to happen in load_stage2_idt() where the IDT is loaded and there the + * VC IDT entry gets setup too in order to handle VCs, one needs a GHCB which + * gets setup with an already setup table which is done in + * initialize_identity_maps() and this is where the circle is complete. + */ void load_stage2_idt(void) { boot_idt_desc.address = (unsigned long)boot_idt; diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 06416113af22..745b418866ea 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -119,11 +119,8 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, /* Include code for early handlers */ #include "../../kernel/sev-shared.c" -static bool early_setup_sev_es(void) +static bool early_setup_ghcb(void) { - if (!sev_es_negotiate_protocol()) - sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_PROT_UNSUPPORTED); - if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -174,7 +171,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) struct es_em_ctxt ctxt; enum es_result result; - if (!boot_ghcb && !early_setup_sev_es()) + if (!boot_ghcb && !early_setup_ghcb()) sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); @@ -246,5 +243,19 @@ void sev_enable(struct boot_params *bp) if (!(sev_status & MSR_AMD64_SEV_ENABLED)) return; + /* Negotiate the GHCB protocol version. */ + if (sev_status & MSR_AMD64_SEV_ES_ENABLED) { + if (!sev_es_negotiate_protocol()) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_PROT_UNSUPPORTED); + } + + /* + * SEV-SNP is supported in v2 of the GHCB spec which mandates support for HV + * features. If SEV-SNP is enabled, then check if the hypervisor supports + * the SEV-SNP features. + */ + if (sev_status & MSR_AMD64_SEV_SNP_ENABLED && !(get_hv_features() & GHCB_HV_FT_SNP)) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + sme_me_mask = BIT_ULL(ebx & 0x3f); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 94f0ea574049..6f037c29a46e 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -60,6 +60,11 @@ /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + /* GHCBData[63:12] */ \ + (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) + +#define GHCB_HV_FT_SNP BIT_ULL(0) #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 @@ -77,6 +82,7 @@ #define SEV_TERM_SET_GEN 0 #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 +#define GHCB_SNP_UNSUPPORTED 2 /* Linux-specific reason codes (used with reason set 1) */ #define SEV_TERM_SET_LINUX 1 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 9b9c190e8c3b..17b75f6ee11a 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -13,7 +13,7 @@ #include <asm/sev-common.h> #define GHCB_PROTOCOL_MIN 1ULL -#define GHCB_PROTOCOL_MAX 1ULL +#define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index efa969325ede..b0ad00f4c1e1 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -108,6 +108,7 @@ #define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 +#define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff /* Exit code reserved for hypervisor/software use */ @@ -218,6 +219,7 @@ { SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ + { SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 91105f5a02a8..4a876e684f67 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -48,6 +48,26 @@ static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) asm volatile("hlt\n" : : : "memory"); } +/* + * The hypervisor features are available from GHCB version 2 onward. + */ +static u64 get_hv_features(void) +{ + u64 val; + + if (ghcb_version < 2) + return 0; + + sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FT_RESP) + return 0; + + return GHCB_MSR_HV_FT_RESP_VAL(val); +} + static bool sev_es_negotiate_protocol(void) { u64 val; diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 19ad09712902..24df739c9c05 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -43,6 +43,9 @@ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); */ static struct ghcb __initdata *boot_ghcb; +/* Bitmap of SEV features supported by the hypervisor */ +static u64 sev_hv_features __ro_after_init; + /* #VC handler runtime per-CPU data */ struct sev_es_runtime_data { struct ghcb ghcb_page; @@ -766,6 +769,18 @@ void __init sev_es_init_vc_handling(void) if (!sev_es_check_cpu_features()) panic("SEV-ES CPU Features missing"); + /* + * SEV-SNP is supported in v2 of the GHCB spec which mandates support for HV + * features. If SEV-SNP is enabled, then check if the hypervisor supports + * the SEV-SNP features. + */ + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) { + sev_hv_features = get_hv_features(); + + if (!(sev_hv_features & GHCB_HV_FT_SNP)) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + } + /* Enable SEV-ES special handling */ static_branch_enable(&sev_es_enable_key);
Version 2 of the GHCB specification added the advertisement of features that are supported by the hypervisor. If hypervisor supports the SEV-SNP then it must set the SEV-SNP features bit to indicate that the base SEV-SNP is supported. Check the SEV-SNP feature while establishing the GHCB, if failed, terminate the guest. Version 2 of GHCB specification adds several new NAEs, most of them are optional except the hypervisor feature. Now that hypervisor feature NAE is implemented, so bump the GHCB maximum support protocol version. While at it, move the GHCB protocol negotiation check from VC exception handler to sev_enable() so that all feature detection happens before the first VC exception. While at it, document why GHCB page cannot be setup from the load_stage2_idt(). Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> --- arch/x86/boot/compressed/idt_64.c | 10 +++++++++- arch/x86/boot/compressed/sev.c | 21 ++++++++++++++++----- arch/x86/include/asm/sev-common.h | 6 ++++++ arch/x86/include/asm/sev.h | 2 +- arch/x86/include/uapi/asm/svm.h | 2 ++ arch/x86/kernel/sev-shared.c | 20 ++++++++++++++++++++ arch/x86/kernel/sev.c | 15 +++++++++++++++ 7 files changed, 69 insertions(+), 7 deletions(-)