From patchwork Wed Apr 6 19:51:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Wahl X-Patchwork-Id: 12804074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72E64C433FE for ; Wed, 6 Apr 2022 21:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235500AbiDFVK5 (ORCPT ); Wed, 6 Apr 2022 17:10:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235192AbiDFVKs (ORCPT ); Wed, 6 Apr 2022 17:10:48 -0400 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBA6C4FC62; Wed, 6 Apr 2022 12:52:29 -0700 (PDT) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 236HOTOA030263; Wed, 6 Apr 2022 19:51:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=deDGlSAGrHXoBiYw4GDNlbX3BQkDTs4ChJEJLjIyjBk=; b=Vq0wppohIWz80El75m92n+8bpgJ0l6U2POQmYUN5YpzYRguN1AqA7EGmH7W7rDmmFu3p 9AaHvM7rrc3vYi5I9UT6xFlXLH9xGG4Kq5d2tLkcEhOlQwgd9zZT1ecNca1anqVdEODn iDc/Vv0yM41s7wus2CUie8xKKKSfjhCBKYEBJtL30qBx6qbFWfn+xxfeCHqkwyWxr6wo vuS3RI8rAXQxtcKncOyVLyAlvc8FP3B81OnjZRMvxaN0JD2Rh22ueaUph3adUqX9USZa rDx56AYLWSsC9Wieub2aFd5FVExXH+1ipBiDQITFd1wyfaI6G1uXxTuIhAT1QU3bXHYG FQ== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3f9cnd2ypj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Apr 2022 19:51:51 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id E778B92; Wed, 6 Apr 2022 19:51:50 +0000 (UTC) Received: from dog.eag.rdlabs.hpecorp.net (dog.eag.rdlabs.hpecorp.net [128.162.243.181]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 4C3C14C; Wed, 6 Apr 2022 19:51:50 +0000 (UTC) Received: by dog.eag.rdlabs.hpecorp.net (Postfix, from userid 200934) id C9F9930087627; Wed, 6 Apr 2022 14:51:49 -0500 (CDT) From: Steve Wahl To: Borislav Petkov , Ingo Molnar , Thomas Gleixner , x86@kernel.org Cc: Mike Travis , Steve Wahl , Andy Shevchenko , Darren Hart , Dimitri Sivanich , "H . Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH v4 2/3] x86/platform/uv: Update TSC sync state for UV5 Date: Wed, 6 Apr 2022 14:51:48 -0500 Message-Id: <20220406195149.228164-3-steve.wahl@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220406195149.228164-1-steve.wahl@hpe.com> References: <20220406195149.228164-1-steve.wahl@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 1DQITyUzCqf0vSmn82lXa7JZfmIFQLy3 X-Proofpoint-GUID: 1DQITyUzCqf0vSmn82lXa7JZfmIFQLy3 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-04-06_11,2022-04-06_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2204060098 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org From: Mike Travis The UV5 platform synchronizes the TSCs among all chassis, and will not proceed to OS boot without achieving synchronization. Previous UV platforms provided a register indicating successful synchronization. This is no longer available on UV5. On this platform TSC_ADJUST should not be reset by the kernel. Signed-off-by: Mike Travis Signed-off-by: Steve Wahl Reviewed-by: Dimitri Sivanich --- v2: Update patch description to be more explanatory. v4: Update patch description to provide better context Removed a pr_debug() and an unrelated whitespace change --- arch/x86/kernel/apic/x2apic_uv_x.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index f5a48e66e4f5..a6e9c2794ef5 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; - /* Different returns from different UV BIOS versions */ + /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ + if (!is_uv(UV2|UV3|UV4)) { + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;