| Message ID | 20231212103644.768460-8-suma.hegde@amd.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | platform/x86: Non-ACPI support for AMD F1A~M0Fh | expand |
Hi, On 12/12/23 11:36, Suma Hegde wrote: > AMD EPYC family 0x1A and Model 0x0-0xF are having different > mailbox message ID offset compared to previous > platforms. In case of ACPI based BIOS, this information will be read > from ACPI table, for non ACPI BIOS, this needs to be #defined. > > Signed-off-by: Suma Hegde <suma.hegde@amd.com> > Co-developed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> > Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Thanks, patch looks good to me: Reviewed-by: Hans de Goede <hdegoede@redhat.com> Regards, Hans > --- > drivers/platform/x86/amd/hsmp.c | 21 ++++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/amd/hsmp.c b/drivers/platform/x86/amd/hsmp.c > index 82bd4189cbd3..2c256a7f50b3 100644 > --- a/drivers/platform/x86/amd/hsmp.c > +++ b/drivers/platform/x86/amd/hsmp.c > @@ -44,6 +44,7 @@ > */ > #define SMN_HSMP_BASE 0x3B00000 > #define SMN_HSMP_MSG_ID 0x0010534 > +#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 > #define SMN_HSMP_MSG_RESP 0x0010980 > #define SMN_HSMP_MSG_DATA 0x00109E0 > > @@ -700,6 +701,15 @@ static int hsmp_cache_proto_ver(u16 sock_ind) > return ret; > } > > +static inline bool is_f1a_m0h(void) > +{ > + if (boot_cpu_data.x86 == 0x1A && > + (boot_cpu_data.x86_model >= 0x00 && boot_cpu_data.x86_model <= 0x0F)) > + return true; > + > + return false; > +} > + > static int initialize_platdev(struct device *dev) > { > int i; > @@ -711,7 +721,16 @@ static int initialize_platdev(struct device *dev) > plat_dev.sock[i].sock_ind = i; > plat_dev.sock[i].dev = dev; > plat_dev.sock[i].mbinfo.base_addr = SMN_HSMP_BASE; > - plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID; > + > + /* > + * This is a tranisitional change from non ACPI to ACPI, only > + * family 0x1A, model 0x00 platform is supported for both ACPI and non ACPI. > + */ > + if (is_f1a_m0h()) > + plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H; > + else > + plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID; > + > plat_dev.sock[i].mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP; > plat_dev.sock[i].mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA; > sema_init(&plat_dev.sock[i].hsmp_sem, 1);
diff --git a/drivers/platform/x86/amd/hsmp.c b/drivers/platform/x86/amd/hsmp.c index 82bd4189cbd3..2c256a7f50b3 100644 --- a/drivers/platform/x86/amd/hsmp.c +++ b/drivers/platform/x86/amd/hsmp.c @@ -44,6 +44,7 @@ */ #define SMN_HSMP_BASE 0x3B00000 #define SMN_HSMP_MSG_ID 0x0010534 +#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 #define SMN_HSMP_MSG_RESP 0x0010980 #define SMN_HSMP_MSG_DATA 0x00109E0 @@ -700,6 +701,15 @@ static int hsmp_cache_proto_ver(u16 sock_ind) return ret; } +static inline bool is_f1a_m0h(void) +{ + if (boot_cpu_data.x86 == 0x1A && + (boot_cpu_data.x86_model >= 0x00 && boot_cpu_data.x86_model <= 0x0F)) + return true; + + return false; +} + static int initialize_platdev(struct device *dev) { int i; @@ -711,7 +721,16 @@ static int initialize_platdev(struct device *dev) plat_dev.sock[i].sock_ind = i; plat_dev.sock[i].dev = dev; plat_dev.sock[i].mbinfo.base_addr = SMN_HSMP_BASE; - plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID; + + /* + * This is a tranisitional change from non ACPI to ACPI, only + * family 0x1A, model 0x00 platform is supported for both ACPI and non ACPI. + */ + if (is_f1a_m0h()) + plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H; + else + plat_dev.sock[i].mbinfo.msg_id_off = SMN_HSMP_MSG_ID; + plat_dev.sock[i].mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP; plat_dev.sock[i].mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA; sema_init(&plat_dev.sock[i].hsmp_sem, 1);