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Peter Anvin" , Michael Turquette , Stephen Boyd Cc: Hans de Goede , platform-driver-x86@vger.kernel.org, x86@kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 1/5] clk: x86: Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_atom.h Date: Mon, 8 Jan 2024 14:02:34 +0100 Message-ID: <20240108130238.540794-2-hdegoede@redhat.com> In-Reply-To: <20240108130238.540794-1-hdegoede@redhat.com> References: <20240108130238.540794-1-hdegoede@redhat.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.5 Move the register defines for the Atom (Bay Trail, Cherry Trail) PMC clocks to include/linux/platform_data/x86/pmc_atom.h. This is a preparation patch to extend the S0i3 readiness checks in drivers/platform/x86/pmc_atom.c with checking that the PMC clocks are off on suspend entry. Note these are added to include/linux/platform_data/x86/pmc_atom.h rather then to include/linux/platform_data/x86/clk-pmc-atom.h because the former already has all the other Atom PMC register defines. Reviewed-by: Ilpo Järvinen Signed-off-by: Hans de Goede Acked-by: Stephen Boyd --- Changes in v2: - This is a new patch in v2 of this series --- drivers/clk/x86/clk-pmc-atom.c | 13 +------------ include/linux/platform_data/x86/pmc_atom.h | 13 +++++++++++++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c index 2974dd0ec6f4..5ec9255e33fa 100644 --- a/drivers/clk/x86/clk-pmc-atom.c +++ b/drivers/clk/x86/clk-pmc-atom.c @@ -11,23 +11,12 @@ #include #include #include +#include #include #include #define PLT_CLK_NAME_BASE "pmc_plt_clk" -#define PMC_CLK_CTL_OFFSET 0x60 -#define PMC_CLK_CTL_SIZE 4 -#define PMC_CLK_NUM 6 -#define PMC_CLK_CTL_GATED_ON_D3 0x0 -#define PMC_CLK_CTL_FORCE_ON 0x1 -#define PMC_CLK_CTL_FORCE_OFF 0x2 -#define PMC_CLK_CTL_RESERVED 0x3 -#define PMC_MASK_CLK_CTL GENMASK(1, 0) -#define PMC_MASK_CLK_FREQ BIT(2) -#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */ -#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */ - struct clk_plt_fixed { struct clk_hw *clk; struct clk_lookup *lookup; diff --git a/include/linux/platform_data/x86/pmc_atom.h b/include/linux/platform_data/x86/pmc_atom.h index b8a701c77fd0..557622ef0390 100644 --- a/include/linux/platform_data/x86/pmc_atom.h +++ b/include/linux/platform_data/x86/pmc_atom.h @@ -43,6 +43,19 @@ BIT_ORED_DEDICATED_IRQ_GPSC | \ BIT_SHARED_IRQ_GPSS) +/* External clk generator settings */ +#define PMC_CLK_CTL_OFFSET 0x60 +#define PMC_CLK_CTL_SIZE 4 +#define PMC_CLK_NUM 6 +#define PMC_CLK_CTL_GATED_ON_D3 0x0 +#define PMC_CLK_CTL_FORCE_ON 0x1 +#define PMC_CLK_CTL_FORCE_OFF 0x2 +#define PMC_CLK_CTL_RESERVED 0x3 +#define PMC_MASK_CLK_CTL GENMASK(1, 0) +#define PMC_MASK_CLK_FREQ BIT(2) +#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */ +#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */ + /* The timers accumulate time spent in sleep state */ #define PMC_S0IR_TMR 0x80 #define PMC_S0I1_TMR 0x84