From patchwork Mon Oct 21 11:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Suma Hegde X-Patchwork-Id: 13843922 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2066.outbound.protection.outlook.com [40.107.220.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3610A1E4929 for ; Mon, 21 Oct 2024 11:15:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729509304; cv=fail; b=E4JwhNmc4PXkF5vIaSdbLGFI0vcEbHRuhYWzOmn9D4unGHTJYPihcXVAGP6W0S6yLrxAV8vhIAU2MU3Q8zRHS+4CmC+wz5PVSrCevcyHsJgAiC/YO9EMTbAzZMXdh93zNnBPNUIxZ3MTwf7BLn4GKFc1HMJHMvcoizQoSW8fm78= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729509304; c=relaxed/simple; bh=Mo67JuSMpWk9mdekEhsUXschXmjlKQEiSUmH0qn+H0A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o2E0JiSl36Zzv2ChEXzsa8Vgd3IAePvsWsS4IbWrkcoAFnD3UPMa6ZzhYCeWQ9Hm+Fx3769F9F0467pN5GsDTSyQT67ndbCqwieg7Rt+X58UlsR0jCHHQ4F4fvWvNOkrGTFJmhhoDJClK9NCr39EcukwS8Nw0ELVxfuecSKWx04= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=kL4Fi3n/; arc=fail smtp.client-ip=40.107.220.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="kL4Fi3n/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lUGr8dbEkcF/uBM2P7lU9thywn4eikYLuq1ics02qqUI12Sl4Z+R8+W5gT3rlVBDl7CRau7t62P8ViTd6DfxXVYPUJrQ3BCUhPobSzS/IErzSYlfBMB5MFa0h38tMitroerxWqoncX4xGYMhaG1lkQgVrw8Kw1+OI3IlkCrOcZdZhAUF7GtgHbuZcA23Z05aillTZuLPpcgJOfD3sDdlv6M4c8OE0AeKbjf+uNfy2ec0zheFtMCTJk4SUf+cXqy3/c/rebyA6+//v6kcmBacGZruYGYw+XLFc8WHM6oys9i9jHCXgiLmuOtsaXx2tYnIwg74zBhOshVVMK9y/Ac6iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QLVtCSBAMiRPcxbBWBfdFr56Waf4Bx56hNkwPJVl02c=; b=whPVpqc4SXwDXscWLMvv87AYV7C3DW3fNiTVOyyEjn5uyBjeOhGR9tK61JbhZpvHjyK8Mkua0cLmBM7xPVbwmiOxTT8XGSic7XkLhbs/OOdmvqUMUKXqJzo8nC/sg8n2yTX+p2iWIdiMYR9fJc5ktCCqP+O66D85VKqFJPTZ0/HO8mE1Qp0RnaW6D2yddk4S2JrjTZLfAkXiO1KyV3omrdQVhhfPzfWxuOC6Yqm6AwFzVZ9SDG7yw6IRsIMqhfn0tlejgSATahTFDJW2Lc5CWcbjXC46mVX8QABYTsoHBrAr6iA2lfwr4SNEY/+UDU/V+Wzei09rc4wzzw04sH08Fg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QLVtCSBAMiRPcxbBWBfdFr56Waf4Bx56hNkwPJVl02c=; b=kL4Fi3n/ENnRV+4J7z/VRkctIGJtSmAA02Bs5D1aN6YnkEoWXOK5YgS6g1qdd6GTQIIZAzg9lKQavrkGRz6wS0XSUZLq+PlMzBEScMbMz4crSNXnZYH2wRrjF9Q5k9Z1cb9Zd4ovisUmIZnBc0yLXYIFKRe64zqa/J8OdXFVUgw= Received: from MN0P223CA0029.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:52b::18) by SA1PR12MB9471.namprd12.prod.outlook.com (2603:10b6:806:458::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.27; Mon, 21 Oct 2024 11:14:59 +0000 Received: from BL02EPF0002992A.namprd02.prod.outlook.com (2603:10b6:208:52b:cafe::88) by MN0P223CA0029.outlook.office365.com (2603:10b6:208:52b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.29 via Frontend Transport; Mon, 21 Oct 2024 11:14:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0002992A.mail.protection.outlook.com (10.167.249.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Mon, 21 Oct 2024 11:14:58 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 21 Oct 2024 06:14:56 -0500 From: Suma Hegde To: CC: , , Suma Hegde , Naveen Krishna Chatradhi Subject: [v10 05/11] platform/x86/amd/hsmp: Move platform device specific code to plat.c Date: Mon, 21 Oct 2024 11:14:22 +0000 Message-ID: <20241021111428.2676884-5-suma.hegde@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241021111428.2676884-1-suma.hegde@amd.com> References: <20241021111428.2676884-1-suma.hegde@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992A:EE_|SA1PR12MB9471:EE_ X-MS-Office365-Filtering-Correlation-Id: b8584963-106e-451c-5e23-08dcf1c1998c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?4E06UfmPJtzCHMdkhCQWDf1Acm47geQ?= =?utf-8?q?pvSutYCQPkKdlLLOB23KwG0V4n13BEqXih8j3nADsPRsKGm3ah1SonMOWXID+6I6n?= =?utf-8?q?O59Fgwb8+Z6wKK1XYJXCB5xQU3ksbxsm8JkwVzDx0ieVOGSKx25EJLm3Z2pF7VjIP?= =?utf-8?q?e16tjdG4T8kty8vErHoP15lOvK4ykk0yw/mRki+nGZPP0gJO9ccbqacNxoP6lyQ5A?= =?utf-8?q?/al1Xp8dq4loxRG8CXATL5R42lQ+gyeCtMkVpfPZJxoVNopAZbKC/z0ydnpoqjs2W?= =?utf-8?q?wFrmpXKxe13I/PTjbsqN3WHQRiayAYsDSt1RcaivuSd4EqRhUV7HG65aLAKOXt+2e?= =?utf-8?q?XJr/yOKZNWP6G7GpLDCm5zPRzeMQEsCLf4UUn4TH00j1cxK/M+a73dB1+eWFpp/Nn?= =?utf-8?q?n0kzlScK225epx1kV7zBXhiVKbnTipTsCCubSuYZftxLrmkA2lkq4OPf0ptYasZAk?= =?utf-8?q?1nGjk8gQcPQIemWacSfEL28JziEY8BuDlG+JgiiZmDUDB5iiCHIdp8aWty0dbEm2Y?= =?utf-8?q?ioAvdicJvDKGa/HP0PCsJArzjem4B75QN8+Deh8y93XnkpHsPcAm5F366z33AxnxX?= =?utf-8?q?YXOoR9Yf9bXtEPgIza8i0NhRQ8D/sW2LNVKapxDfgKDOElgp6Pzk8BTAiUsXTXvNG?= =?utf-8?q?a3hiCUvTkekJovS5eYT01Rkk+tjzZ84d6x9BYg4KCIBTbNAD8hNKyU54u44ffGZDq?= =?utf-8?q?xycDbpCEisoQR+33TIklKacZvwCByRRh3GGh+vvoXfZ/mUP03jT79VpItjlEB/vc1?= =?utf-8?q?0LPcxSLsDk+DHJbPS0dKn5gUUv/B5YouhYnJHthfhl4yFncN3Gf40gyXwfomvEZXv?= =?utf-8?q?dl84V6qD2lzZyf7fgT9ig+DtEvIcyaxEu9Xa/L61JswBkdAPt9Si+clE1oa8f5myz?= =?utf-8?q?dh7zplRVRfAVjG2VuYhH2ZTqxGdyGbqZWeoim45GfZ0hqmDVA/9usCdBY6eXdShC6?= =?utf-8?q?710YTjOP7Agq4Dx+zThhpqo6SfilX7Rajq2IYJC+fpeHtykumluxSekmbLS4RTjAp?= =?utf-8?q?aojjz2m+q4QqhNsOh3+exl2mw7n7Z5srIMqgL/NeBpw2GT363jxtST7x4TlyoIFtU?= =?utf-8?q?Pvmp07qaPVLMthEcLyhu9QJ74wb2o8iJgH4y7S3Jvszid8prp6yNuJsZSxTPZMX0i?= =?utf-8?q?hs//tB3iKYuqoG5FldWmqoAqN6OuBkhwuuFTO23uTG403e0FGtKOwAIIKi1fPkFrV?= =?utf-8?q?JQTlRzJoehfq3eGmdGsfFSA8+P1y+DUyZHAbZ3WSKIyQtIr4cFHIUiRmvuPwxiWzf?= =?utf-8?q?lhZUcybeSiZvPqhvHdYaRxR4rcEtIw6oUTBQfdUpLr6MQ0rr5cCBL04SF6N93NgUU?= =?utf-8?q?w+GVoH2LeYf3Df9rVxYMAF4XyB5sbrALiw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2024 11:14:58.6238 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8584963-106e-451c-5e23-08dcf1c1998c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9471 An upcoming change splits HSMP driver into ACPI and platform device variants. Prepare for the split by moving platform device part to plat.c. No functinality/logical changes. Common code which can be used by ACPI and platform device remains in hsmp.c. ACPI code in hsmp.c will be moved to acpi.c in next patch. Signed-off-by: Suma Hegde Reviewed-by: Naveen Krishna Chatradhi Reviewed-by: Ilpo Järvinen --- Changes since v9: None Changes since v8: None Changes since v7: None Changes since v6: None Changes since v5: None Changes since v4: 1. Update commit description. 2. Add "Reviewed-by: Ilpo Järvinen " Changes since v3: 1. module init, exit code, probe, remove functions are kept back in hsmp.c not added to plat.c in this patch, as per review comment. Changes since v2: None Changes since v1: 1. Include new header file device.h in plat.c 2. Arrange headers in alphabetical order 3. Add an empty line between asm/ and linux/ headers drivers/platform/x86/amd/hsmp/Makefile | 2 +- drivers/platform/x86/amd/hsmp/hsmp.c | 138 ++----------------------- drivers/platform/x86/amd/hsmp/hsmp.h | 14 +++ drivers/platform/x86/amd/hsmp/plat.c | 136 ++++++++++++++++++++++++ 4 files changed, 161 insertions(+), 129 deletions(-) create mode 100644 drivers/platform/x86/amd/hsmp/plat.c diff --git a/drivers/platform/x86/amd/hsmp/Makefile b/drivers/platform/x86/amd/hsmp/Makefile index fda64906a5e8..fb8ba04b2f0d 100644 --- a/drivers/platform/x86/amd/hsmp/Makefile +++ b/drivers/platform/x86/amd/hsmp/Makefile @@ -5,4 +5,4 @@ # obj-$(CONFIG_AMD_HSMP) += amd_hsmp.o -amd_hsmp-objs := hsmp.o +amd_hsmp-objs := hsmp.o plat.o diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/amd/hsmp/hsmp.c index 9ed1fc0aeb00..6da7c6189020 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -40,45 +39,12 @@ #define HSMP_WR true #define HSMP_RD false -/* - * To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox - * register into the SMN_INDEX register, and reads/writes the SMN_DATA reg. - * Below are required SMN address for HSMP Mailbox register offsets in SMU address space - */ -#define SMN_HSMP_BASE 0x3B00000 -#define SMN_HSMP_MSG_ID 0x0010534 -#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 -#define SMN_HSMP_MSG_RESP 0x0010980 -#define SMN_HSMP_MSG_DATA 0x00109E0 - -#define HSMP_INDEX_REG 0xc4 -#define HSMP_DATA_REG 0xc8 - /* These are the strings specified in ACPI table */ #define MSG_IDOFF_STR "MsgIdOffset" #define MSG_ARGOFF_STR "MsgArgOffset" #define MSG_RESPOFF_STR "MsgRspOffset" -static struct hsmp_plat_device plat_dev; - -static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, - u32 *value, bool write) -{ - int ret; - - if (!sock->root) - return -ENODEV; - - ret = pci_write_config_dword(sock->root, HSMP_INDEX_REG, - sock->mbinfo.base_addr + offset); - if (ret) - return ret; - - ret = (write ? pci_write_config_dword(sock->root, HSMP_DATA_REG, *value) - : pci_read_config_dword(sock->root, HSMP_DATA_REG, value)); - - return ret; -} +struct hsmp_plat_device plat_dev; static int amd_hsmp_acpi_rdwr(struct hsmp_socket *sock, u32 offset, u32 *value, bool write) @@ -248,7 +214,7 @@ int hsmp_send_message(struct hsmp_message *msg) } EXPORT_SYMBOL_GPL(hsmp_send_message); -static int hsmp_test(u16 sock_ind, u32 value) +int hsmp_test(u16 sock_ind, u32 value) { struct hsmp_message msg = { 0 }; int ret; @@ -516,9 +482,9 @@ static int hsmp_parse_acpi_table(struct device *dev, u16 sock_ind) return hsmp_read_acpi_dsd(sock); } -static ssize_t hsmp_metric_tbl_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, char *buf, - loff_t off, size_t count) +ssize_t hsmp_metric_tbl_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count) { struct hsmp_socket *sock = bin_attr->private; struct hsmp_message msg = { 0 }; @@ -577,8 +543,8 @@ static int hsmp_get_tbl_dram_base(u16 sock_ind) return 0; } -static umode_t hsmp_is_sock_attr_visible(struct kobject *kobj, - struct bin_attribute *battr, int id) +umode_t hsmp_is_sock_attr_visible(struct kobject *kobj, + struct bin_attribute *battr, int id) { if (plat_dev.proto_ver == HSMP_PROTO_VER6) return battr->attr.mode; @@ -607,8 +573,8 @@ static int hsmp_init_metric_tbl_bin_attr(struct bin_attribute **hattrs, u16 sock /* One bin sysfs for metrics table */ #define NUM_HSMP_ATTRS 1 -static int hsmp_create_attr_list(struct attribute_group *attr_grp, - struct device *dev, u16 sock_ind) +int hsmp_create_attr_list(struct attribute_group *attr_grp, + struct device *dev, u16 sock_ind) { struct bin_attribute **hsmp_bin_attrs; @@ -624,36 +590,6 @@ static int hsmp_create_attr_list(struct attribute_group *attr_grp, return hsmp_init_metric_tbl_bin_attr(hsmp_bin_attrs, sock_ind); } -static int hsmp_create_non_acpi_sysfs_if(struct device *dev) -{ - const struct attribute_group **hsmp_attr_grps; - struct attribute_group *attr_grp; - u16 i; - - hsmp_attr_grps = devm_kcalloc(dev, plat_dev.num_sockets + 1, - sizeof(*hsmp_attr_grps), - GFP_KERNEL); - if (!hsmp_attr_grps) - return -ENOMEM; - - /* Create a sysfs directory for each socket */ - for (i = 0; i < plat_dev.num_sockets; i++) { - attr_grp = devm_kzalloc(dev, sizeof(struct attribute_group), - GFP_KERNEL); - if (!attr_grp) - return -ENOMEM; - - snprintf(plat_dev.sock[i].name, HSMP_ATTR_GRP_NAME_SIZE, "socket%u", (u8)i); - attr_grp->name = plat_dev.sock[i].name; - attr_grp->is_bin_visible = hsmp_is_sock_attr_visible; - hsmp_attr_grps[i] = attr_grp; - - hsmp_create_attr_list(attr_grp, dev, i); - } - - return device_add_groups(dev, hsmp_attr_grps); -} - static int hsmp_create_acpi_sysfs_if(struct device *dev) { struct attribute_group *attr_grp; @@ -677,7 +613,7 @@ static int hsmp_create_acpi_sysfs_if(struct device *dev) return devm_device_add_group(dev, attr_grp); } -static int hsmp_cache_proto_ver(u16 sock_ind) +int hsmp_cache_proto_ver(u16 sock_ind) { struct hsmp_message msg = { 0 }; int ret; @@ -693,60 +629,6 @@ static int hsmp_cache_proto_ver(u16 sock_ind) return ret; } -static inline bool is_f1a_m0h(void) -{ - if (boot_cpu_data.x86 == 0x1A && boot_cpu_data.x86_model <= 0x0F) - return true; - - return false; -} - -static int init_platform_device(struct device *dev) -{ - struct hsmp_socket *sock; - int ret, i; - - for (i = 0; i < plat_dev.num_sockets; i++) { - if (!node_to_amd_nb(i)) - return -ENODEV; - sock = &plat_dev.sock[i]; - sock->root = node_to_amd_nb(i)->root; - sock->sock_ind = i; - sock->dev = dev; - sock->mbinfo.base_addr = SMN_HSMP_BASE; - sock->amd_hsmp_rdwr = amd_hsmp_pci_rdwr; - - /* - * This is a transitional change from non-ACPI to ACPI, only - * family 0x1A, model 0x00 platform is supported for both ACPI and non-ACPI. - */ - if (is_f1a_m0h()) - sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H; - else - sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID; - - sock->mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP; - sock->mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA; - sema_init(&sock->hsmp_sem, 1); - - /* Test the hsmp interface on each socket */ - ret = hsmp_test(i, 0xDEADBEEF); - if (ret) { - dev_err(dev, "HSMP test message failed on Fam:%x model:%x\n", - boot_cpu_data.x86, boot_cpu_data.x86_model); - dev_err(dev, "Is HSMP disabled in BIOS ?\n"); - return ret; - } - ret = hsmp_cache_proto_ver(i); - if (ret) { - dev_err(dev, "Failed to read HSMP protocol version\n"); - return ret; - } - } - - return 0; -} - static const struct acpi_device_id amd_hsmp_acpi_ids[] = { {ACPI_HSMP_DEVICE_HID, 0}, {} diff --git a/drivers/platform/x86/amd/hsmp/hsmp.h b/drivers/platform/x86/amd/hsmp/hsmp.h index d54b9681d514..d59a9efb4799 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.h +++ b/drivers/platform/x86/amd/hsmp/hsmp.h @@ -55,4 +55,18 @@ struct hsmp_plat_device { bool is_acpi_device; bool is_probed; }; + +extern struct hsmp_plat_device plat_dev; + +ssize_t hsmp_metric_tbl_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count); +int hsmp_create_non_acpi_sysfs_if(struct device *dev); +int hsmp_cache_proto_ver(u16 sock_ind); +umode_t hsmp_is_sock_attr_visible(struct kobject *kobj, + struct bin_attribute *battr, int id); +int hsmp_create_attr_list(struct attribute_group *attr_grp, + struct device *dev, u16 sock_ind); +int hsmp_test(u16 sock_ind, u32 value); +int init_platform_device(struct device *dev); #endif /* HSMP_H */ diff --git a/drivers/platform/x86/amd/hsmp/plat.c b/drivers/platform/x86/amd/hsmp/plat.c new file mode 100644 index 000000000000..85a104859acd --- /dev/null +++ b/drivers/platform/x86/amd/hsmp/plat.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD HSMP Platform Driver + * Copyright (c) 2024, AMD. + * All Rights Reserved. + * + * This file provides platform device implementations. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include + +#include +#include +#include + +#include "hsmp.h" + +/* + * To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox + * register into the SMN_INDEX register, and reads/writes the SMN_DATA reg. + * Below are required SMN address for HSMP Mailbox register offsets in SMU address space + */ +#define SMN_HSMP_BASE 0x3B00000 +#define SMN_HSMP_MSG_ID 0x0010534 +#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 +#define SMN_HSMP_MSG_RESP 0x0010980 +#define SMN_HSMP_MSG_DATA 0x00109E0 + +#define HSMP_INDEX_REG 0xc4 +#define HSMP_DATA_REG 0xc8 + +static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, + u32 *value, bool write) +{ + int ret; + + if (!sock->root) + return -ENODEV; + + ret = pci_write_config_dword(sock->root, HSMP_INDEX_REG, + sock->mbinfo.base_addr + offset); + if (ret) + return ret; + + ret = (write ? pci_write_config_dword(sock->root, HSMP_DATA_REG, *value) + : pci_read_config_dword(sock->root, HSMP_DATA_REG, value)); + + return ret; +} + +int hsmp_create_non_acpi_sysfs_if(struct device *dev) +{ + const struct attribute_group **hsmp_attr_grps; + struct attribute_group *attr_grp; + u16 i; + + hsmp_attr_grps = devm_kcalloc(dev, plat_dev.num_sockets + 1, + sizeof(*hsmp_attr_grps), + GFP_KERNEL); + if (!hsmp_attr_grps) + return -ENOMEM; + + /* Create a sysfs directory for each socket */ + for (i = 0; i < plat_dev.num_sockets; i++) { + attr_grp = devm_kzalloc(dev, sizeof(struct attribute_group), + GFP_KERNEL); + if (!attr_grp) + return -ENOMEM; + + snprintf(plat_dev.sock[i].name, HSMP_ATTR_GRP_NAME_SIZE, "socket%u", (u8)i); + attr_grp->name = plat_dev.sock[i].name; + attr_grp->is_bin_visible = hsmp_is_sock_attr_visible; + hsmp_attr_grps[i] = attr_grp; + + hsmp_create_attr_list(attr_grp, dev, i); + } + + return device_add_groups(dev, hsmp_attr_grps); +} + +static inline bool is_f1a_m0h(void) +{ + if (boot_cpu_data.x86 == 0x1A && boot_cpu_data.x86_model <= 0x0F) + return true; + + return false; +} + +int init_platform_device(struct device *dev) +{ + struct hsmp_socket *sock; + int ret, i; + + for (i = 0; i < plat_dev.num_sockets; i++) { + if (!node_to_amd_nb(i)) + return -ENODEV; + sock = &plat_dev.sock[i]; + sock->root = node_to_amd_nb(i)->root; + sock->sock_ind = i; + sock->dev = dev; + sock->mbinfo.base_addr = SMN_HSMP_BASE; + sock->amd_hsmp_rdwr = amd_hsmp_pci_rdwr; + + /* + * This is a transitional change from non-ACPI to ACPI, only + * family 0x1A, model 0x00 platform is supported for both ACPI and non-ACPI. + */ + if (is_f1a_m0h()) + sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H; + else + sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID; + + sock->mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP; + sock->mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA; + sema_init(&sock->hsmp_sem, 1); + + /* Test the hsmp interface on each socket */ + ret = hsmp_test(i, 0xDEADBEEF); + if (ret) { + dev_err(dev, "HSMP test message failed on Fam:%x model:%x\n", + boot_cpu_data.x86, boot_cpu_data.x86_model); + dev_err(dev, "Is HSMP disabled in BIOS ?\n"); + return ret; + } + + ret = hsmp_cache_proto_ver(i); + if (ret) { + dev_err(dev, "Failed to read HSMP protocol version\n"); + return ret; + } + } + + return 0; +}