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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v4 04/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Mon, 21 Oct 2024 13:02:43 -0500 Message-ID: <20241021180252.3531-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241021180252.3531-1-mario.limonciello@amd.com> References: <20241021180252.3531-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D0:EE_|DM4PR12MB6662:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e79b3b1-c9cd-413d-796b-08dcf1faa580 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: /ohL2zAN7BM+9VamhhrrSs/a7YfcR9zPZK7SJeFEw9uhCyXPiYUeyrSFAoYFjFQqBsxKnk6370nuKEz33sFdJrlmbsR2GUCmlB2VUPV4VmYfBlABLGZx1omZgCWuUTpEG4T9UqEAi5Du/RZxauxvLxBtj00J09/iCTgdwGqW1m/I4QHeHptOp321eLtdlUx9av5GnfJ68KjfTNyyRjpskGx442su4ijW9MWn9AlB1ywdjRc9lNnsGvlFVfn085sM75nEwusw7qN023C9YKlaMzeMiVDfjVOt1pSxdzDSna+UKeF3KKN8nBn+ure81kBTAiUPTh+jMMRylJ9UTV3olMhvFpbXzB26qUSjDVLRnDnU6K8lCL4bdsdUlgF/et8tagj3FtEl2J44ETWznARU59aQbmCLIP1H8EO5NG8NrX8Dp4TRnvmkgAvszMNb2ZJPFGPrLoefKAUg0KQ0Eo42BptmEYXXNB0iI3GDPWH00cVcSnEueppOoh+1hRhFp9bPedGdhozT08SFMkCBxfZ5DxwO1cXXdLE0iuh4zVMh28oQNru/1u3v4YmvxMx4hz00SkVfi1ZmWz3UxrqwCiUtsCHCao6Qq04CpZIDxJgZU+sCVs6qodVJmQNxPBuqlsdT0OF0Ti3cxXQXnyoVhdSwC199Z+VhvEM93v3Zpo34b2ZX1P9PGeR02ZxgqY6LiriX9dXTyTusPqXlWEbcghwm3sfIquKH9Dg+6u3DMgc8Ji2F27/1XVziKwQPRliAleR9Xdy/U6w7E6oYWvn+JMQHx7pPVXg0LOxBmoWvKp8fKKdUEGtYNyE1LIxKT8WtZ2T8JJvm6Ba56XMaKVBFy4CNx1Q9+gdAD6pC9/xqYW76ldJuG+k+bmHhiF3HTHD6nrCH1qgm300i11SQlmXwkv/iRd85Kts6S+X5P/RmCg1KPtD2/qGPo8RVZtCx6PDQlr0jDwZaRjKp9S26hM5mkQLWmMJPh04s4a2dqOCHPsLwnWsg0TMBwCWfdYvkJN9Md2dHYra4rZ4QY7q0s3MP2FdcvdNbxTjnTLMAjxf+zVBbzwBelTDKA66QpbxFuN3BeRotbL4nlt46ZhyEGNx6eBISUcmUTbfg5tNzNChm3k0ulb6c/p9wDnSoM5VfqCrzMVAGTwSe6BJj82+SH7/o4aBvnqncy151kcy0pc4anr0eIhdljlBLhoqFAr9JXL9EtUc/ZM5pLH2vQFVkrNycoAnWwIGvq6896iGFvjbsXPJJApLNk8tTqrH8JWi+7pnBEdIBqeWdF+RnbBLhgOSkhyELym53ncQap5IRmuPT/6CivHTvph/2Uk+17FCYF9BH7gwF5CDi1STWu5Bzx5OHGz+sBS7yw0YWyWlCgBK0DxgLite00pQV60dJO1quqdap6HrlFqz5XD6DKwq73O0kIvjORQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2024 18:03:19.9139 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e79b3b1-c9cd-413d-796b-08dcf1faa580 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6662 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6db..0cd5ffe50f4a4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e