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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075EF.mail.protection.outlook.com (10.167.249.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Mon, 28 Oct 2024 07:05:11 +0000 Received: from airavat.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Oct 2024 02:05:08 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH 4/8] platform/x86/amd/pmc: Isolate STB code changes to a new file Date: Mon, 28 Oct 2024 12:34:34 +0530 Message-ID: <20241028070438.1548737-5-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028070438.1548737-1-Shyam-sundar.S-k@amd.com> References: <20241028070438.1548737-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EF:EE_|MW6PR12MB8835:EE_ X-MS-Office365-Filtering-Correlation-Id: cec908c2-45ee-4acf-b3d5-08dcf71eddb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: 4ARQEB9Nb7GKYPpFEB9Q6k2gHbaM9quyBg6oYuSz9U+qyINXQ0XYp5U6KE8fhnOlaI+65Fyodij8iifZIOCf2i4nbosKWsU7USp2go4lADYz3Ac99jhZgMakjSmcDAsyFH57CB+nYutCIBx75vnMI5efESQ5Qi00+hBJH/THKqefXAONxQI18alnZ+xZcwZwmKHEJE7Spn9MHouZ/W30On0F3wBsp8bu2C/NL7rzjuaw66STUS9WpY+KcDYJa2R0G09522uGGAKMR9E5kjgTbLCsJTnpRwTDP2Da/28IOCtmi/mm37fTzokG1/rc6AGhIf8v1YIGk6jlSXU0R2pN149p4tjK002hqbAktbbQQ+IVwErRKG+dhvWRtMj3BdYlWNY6B8qt11l++uHzfxO0UZx4T5CcgzV73RxzduUurPlTwatcjJrJ+7q1lYIR54Q+zguRIGm/F25VxUZD70E5iI//Gd/QiWT7PtuCaMt5fqM5qI93JKVXbU8K5mFcntFQlDVENouYbvoZSpXkCi305QFZrxX/A2ScGfPXJXAsHigHkCPyQTWT2gYMMxyTXBP2yakki7wGp6+sS/czOFfJqoD3KwKHMLE4ZhRMAKQB2rrZANXg9R8gWGfp8Cc5jXczppvGqGsbgOiAe7NXHsAYnqEeA5NVrp0TybSMilqx4UMwMY5tCXIaE+ZWEdCoYuTNTEfTimp3Sfyf3EWpZgoP3axQ4i/eExSyEhgBe7mME9nxVkNL5Bio2OJOronyZmXkBi5wt+9s0PC4x98mkyX0Ex369lU9pYL4MOiyxxtHPu4UQPwfuVpexES7P5s3P7Q7bPx5dz3EWuG1M9AMZoxZc40/lUY2zLMp/PQFo6jN++DBbCMBHAJNkPJ453JUfcuVORlip/pHwYPvIJGXd3ximvlYbPXipE1tZCymO9+7Yz7FX5kNZQrLNGPNyUPm7TQcC9gwgFW+SL1jX0wHATPoXNv9iafek+GZ3VjyeM7i5G7z5w4jJDMjofGQwMKYW7Vnoiy/VgnQXcnz+ajSINxD4f/ZuTwv+XoORhc+k3zmxqa21ARexVxg/+9GaIVEOtMlbThttcXkr86SOKQTY8A7EH0sdxh6GlQL/DSt8yP6J7dN1+56+a6/+lHdpqO3qzTrg7UZNxM1/Ivb8WVeVRkOcOzoenn22XIU7Y0e5k0G7zTzJO0vOlk4vlDVp0Mqru16xyGAcxzgc0H+twaKHRvgk5ym9WzZJet0zfhoO2Gq4mGiLaDeFAl34X44Bm5GguZGvN0HPzpaW/3IdrGCWKf+S63oPYDBxs0jx8DNubPHJ36Jc/ot4DcN7PBvsZrNjPcW6zS3DNeVJTubO1WoNEYiQx3ZUX3dutcc5oS/rBfidBLonK9Xl7jqq9pBmrRfa+s5557GYlkJ7tEOefk4HA7W9Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 07:05:11.9219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cec908c2-45ee-4acf-b3d5-08dcf71eddb9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8835 Since S2D (Spill to DRAM) uses different message port offsets compared to PMC message offsets for communication with PMFW, relocate the S2D macros from pmc.c to a new file, mp1_stb.c, for better code organization. Following this change, it is logical to introduce a new structure, "struct stb_arg," to pass the message, argument, and response offset details to PMFW via the amd_pmc_send_cmd() call. Additionally, move the s2d_msg_id member from amd_pmc_dev into the new structure. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmc/mp1_stb.c | 33 +++++++++++++++++--------- drivers/platform/x86/amd/pmc/pmc.c | 12 +++++----- drivers/platform/x86/amd/pmc/pmc.h | 14 ++++++----- 3 files changed, 36 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/amd/pmc/mp1_stb.c b/drivers/platform/x86/amd/pmc/mp1_stb.c index 2b06861c479b..1501793b9281 100644 --- a/drivers/platform/x86/amd/pmc/mp1_stb.c +++ b/drivers/platform/x86/amd/pmc/mp1_stb.c @@ -31,6 +31,11 @@ #define STB_FORCE_FLUSH_DATA 0xCF #define FIFO_SIZE 4096 +/* STB S2D(Spill to DRAM) has different message port offset */ +#define AMD_S2D_REGISTER_MESSAGE 0xA20 +#define AMD_S2D_REGISTER_RESPONSE 0xA80 +#define AMD_S2D_REGISTER_ARGUMENT 0xA88 + static bool enable_stb; module_param(enable_stb, bool, 0644); MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); @@ -176,7 +181,7 @@ static int amd_stb_debugfs_open_v2(struct inode *inode, struct file *filp) return amd_stb_handle_efr(filp); /* Get the num_samples to calculate the last push location */ - ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true); + ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->stb_arg.s2d_msg_id, true); /* Clear msg_port for other SMU operation */ dev->msg_port = MSG_PORT_PMC; if (ret) { @@ -239,18 +244,24 @@ static bool amd_is_stb_supported(struct amd_pmc_dev *dev) switch (dev->cpu_id) { case AMD_CPU_ID_YC: case AMD_CPU_ID_CB: - dev->s2d_msg_id = 0xBE; - return true; + dev->stb_arg.s2d_msg_id = 0xBE; + break; case AMD_CPU_ID_PS: - dev->s2d_msg_id = 0x85; - return true; + dev->stb_arg.s2d_msg_id = 0x85; + break; case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: - dev->s2d_msg_id = 0xDE; - return true; + dev->stb_arg.s2d_msg_id = 0xDE; + break; default: return false; } + + dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE; + dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT; + dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE; + + return true; } int amd_s2d_init(struct amd_pmc_dev *dev) @@ -273,18 +284,18 @@ int amd_s2d_init(struct amd_pmc_dev *dev) /* Spill to DRAM feature uses separate SMU message port */ dev->msg_port = MSG_PORT_S2D; - amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true); + amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->stb_arg.s2d_msg_id, true); if (size != S2D_TELEMETRY_BYTES_MAX) return -EIO; /* Get DRAM size */ - ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true); + ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->stb_arg.s2d_msg_id, true); if (ret || !dev->dram_size) dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX; /* Get STB DRAM address */ - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true); - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true); + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->stb_arg.s2d_msg_id, true); + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->stb_arg.s2d_msg_id, true); stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index 8e7c87505327..f9900a03391a 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -450,9 +450,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) u32 value, message, argument, response; if (dev->msg_port) { - message = AMD_S2D_REGISTER_MESSAGE; - argument = AMD_S2D_REGISTER_ARGUMENT; - response = AMD_S2D_REGISTER_RESPONSE; + message = dev->stb_arg.msg; + argument = dev->stb_arg.arg; + response = dev->stb_arg.resp; } else { message = dev->smu_msg; argument = AMD_PMC_REGISTER_ARGUMENT; @@ -477,9 +477,9 @@ int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool r mutex_lock(&dev->lock); if (dev->msg_port) { - message = AMD_S2D_REGISTER_MESSAGE; - argument = AMD_S2D_REGISTER_ARGUMENT; - response = AMD_S2D_REGISTER_RESPONSE; + message = dev->stb_arg.msg; + argument = dev->stb_arg.arg; + response = dev->stb_arg.resp; } else { message = dev->smu_msg; argument = AMD_PMC_REGISTER_ARGUMENT; diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h index 7e7f9170124c..d3c6730ebcd7 100644 --- a/drivers/platform/x86/amd/pmc/pmc.h +++ b/drivers/platform/x86/amd/pmc/pmc.h @@ -25,6 +25,13 @@ struct amd_mp2_dev { bool is_stb_data; }; +struct stb_arg { + u32 s2d_msg_id; + u32 msg; + u32 arg; + u32 resp; +}; + struct amd_pmc_dev { void __iomem *regbase; void __iomem *smu_virt_addr; @@ -36,7 +43,6 @@ struct amd_pmc_dev { u32 active_ips; u32 dram_size; u32 num_ips; - u32 s2d_msg_id; u32 smu_msg; /* SMU version information */ u8 smu_program; @@ -50,6 +56,7 @@ struct amd_pmc_dev { struct quirk_entry *quirks; bool disable_8042_wakeup; struct amd_mp2_dev *mp2; + struct stb_arg stb_arg; }; void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev); @@ -70,11 +77,6 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev); #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 #define PCI_DEVICE_ID_AMD_MP2_STB 0x172c -/* STB S2D(Spill to DRAM) has different message port offset */ -#define AMD_S2D_REGISTER_MESSAGE 0xA20 -#define AMD_S2D_REGISTER_RESPONSE 0xA80 -#define AMD_S2D_REGISTER_ARGUMENT 0xA88 - int amd_s2d_init(struct amd_pmc_dev *dev); int amd_write_stb(struct amd_pmc_dev *dev, u32 data); int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);