| Message ID | 20241029155440.3499273-8-Shyam-sundar.S-k@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | platform/x86/amd/pmc: Updates to AMD PMC driver | expand |
On 10/29/2024 10:54, Shyam Sundar S K wrote: > Previously, AMD's Ryzen Desktop SoCs did not include support for STB. > However, to accommodate this recent change, PMFW has implemented a new > message port pair mechanism for handling messages, arguments, and > responses, specifically designed for distinguishing from Mobile SoCs. > Therefore, it is necessary to update the driver to properly handle this > incoming change. > > Add a new function amd_stb_update_args() to simply the arguments that > needs to be passed between S2D supported Mobile SoCs vs Desktop SoCs. > > Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> > Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> > Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> > --- > drivers/platform/x86/amd/pmc/mp1_stb.c | 31 +++++++++++++++++++++----- > 1 file changed, 26 insertions(+), 5 deletions(-) > > diff --git a/drivers/platform/x86/amd/pmc/mp1_stb.c b/drivers/platform/x86/amd/pmc/mp1_stb.c > index 917c111b31c9..6a3cfcbb614e 100644 > --- a/drivers/platform/x86/amd/pmc/mp1_stb.c > +++ b/drivers/platform/x86/amd/pmc/mp1_stb.c > @@ -36,6 +36,11 @@ > #define AMD_S2D_REGISTER_RESPONSE 0xA80 > #define AMD_S2D_REGISTER_ARGUMENT 0xA88 > > +/* STB S2D(Spill to DRAM) message port offset for 44h model */ > +#define AMD_GNR_REGISTER_MESSAGE 0x524 > +#define AMD_GNR_REGISTER_RESPONSE 0x570 > +#define AMD_GNR_REGISTER_ARGUMENT 0xA40 > + > static bool enable_stb; > module_param(enable_stb, bool, 0644); > MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); > @@ -239,12 +244,31 @@ static const struct file_operations amd_stb_debugfs_fops_v2 = { > .release = amd_stb_debugfs_release_v2, > }; > > +static void amd_stb_update_args(struct amd_pmc_dev *dev) > +{ > + if (cpu_feature_enabled(X86_FEATURE_ZEN5)) > + switch (boot_cpu_data.x86_model) { > + case 0x44: > + dev->stb_arg.msg = AMD_GNR_REGISTER_MESSAGE; > + dev->stb_arg.arg = AMD_GNR_REGISTER_ARGUMENT; > + dev->stb_arg.resp = AMD_GNR_REGISTER_RESPONSE; > + return; > + } > + > + dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE; > + dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT; > + dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE; > +} > + > static bool amd_is_stb_supported(struct amd_pmc_dev *dev) > { > switch (dev->cpu_id) { > case AMD_CPU_ID_YC: > case AMD_CPU_ID_CB: > - dev->stb_arg.s2d_msg_id = 0xBE; > + if (boot_cpu_data.x86_model == 0x44) > + dev->stb_arg.s2d_msg_id = 0x9B; > + else > + dev->stb_arg.s2d_msg_id = 0xBE; > break; > case AMD_CPU_ID_PS: > dev->stb_arg.s2d_msg_id = 0x85; > @@ -260,10 +284,7 @@ static bool amd_is_stb_supported(struct amd_pmc_dev *dev) > return false; > } > > - dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE; > - dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT; > - dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE; > - > + amd_stb_update_args(dev); > return true; > } >
diff --git a/drivers/platform/x86/amd/pmc/mp1_stb.c b/drivers/platform/x86/amd/pmc/mp1_stb.c index 917c111b31c9..6a3cfcbb614e 100644 --- a/drivers/platform/x86/amd/pmc/mp1_stb.c +++ b/drivers/platform/x86/amd/pmc/mp1_stb.c @@ -36,6 +36,11 @@ #define AMD_S2D_REGISTER_RESPONSE 0xA80 #define AMD_S2D_REGISTER_ARGUMENT 0xA88 +/* STB S2D(Spill to DRAM) message port offset for 44h model */ +#define AMD_GNR_REGISTER_MESSAGE 0x524 +#define AMD_GNR_REGISTER_RESPONSE 0x570 +#define AMD_GNR_REGISTER_ARGUMENT 0xA40 + static bool enable_stb; module_param(enable_stb, bool, 0644); MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); @@ -239,12 +244,31 @@ static const struct file_operations amd_stb_debugfs_fops_v2 = { .release = amd_stb_debugfs_release_v2, }; +static void amd_stb_update_args(struct amd_pmc_dev *dev) +{ + if (cpu_feature_enabled(X86_FEATURE_ZEN5)) + switch (boot_cpu_data.x86_model) { + case 0x44: + dev->stb_arg.msg = AMD_GNR_REGISTER_MESSAGE; + dev->stb_arg.arg = AMD_GNR_REGISTER_ARGUMENT; + dev->stb_arg.resp = AMD_GNR_REGISTER_RESPONSE; + return; + } + + dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE; + dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT; + dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE; +} + static bool amd_is_stb_supported(struct amd_pmc_dev *dev) { switch (dev->cpu_id) { case AMD_CPU_ID_YC: case AMD_CPU_ID_CB: - dev->stb_arg.s2d_msg_id = 0xBE; + if (boot_cpu_data.x86_model == 0x44) + dev->stb_arg.s2d_msg_id = 0x9B; + else + dev->stb_arg.s2d_msg_id = 0xBE; break; case AMD_CPU_ID_PS: dev->stb_arg.s2d_msg_id = 0x85; @@ -260,10 +284,7 @@ static bool amd_is_stb_supported(struct amd_pmc_dev *dev) return false; } - dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE; - dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT; - dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE; - + amd_stb_update_args(dev); return true; }