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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v6 09/12] x86/process: Clear hardware feedback history for AMD processors Date: Mon, 4 Nov 2024 11:54:04 -0600 Message-ID: <20241104175407.19546-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104175407.19546-1-mario.limonciello@amd.com> References: <20241104175407.19546-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|SA0PR12MB7464:EE_ X-MS-Office365-Filtering-Correlation-Id: 426026ec-ba40-43c0-adeb-08dcfcf9c690 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: Ydc6xCSzCHICID9q0XXgAgkWFhfr7bqpuwECWq3TghETtVW2DhPs5ZoOYuDMcNrqM/h8hwaWbQ0lhJ2RlpF6nRvSNMCB44nBF0rGs+o1Kik714Qwsk5J0DPsSGnt7fT905lVXFfA3kRA4c3n3Zw4hHLdUfikTEwoTdSsUDzyWTN3q1AJ51HhtJAOk/N9OvszqbSyCX2tjG1IJhgKY+ZCafDELdVm2L7R23Eu03d+jZmFVJITt3v07j5zCsLKP3KtzYMwC9BgMj+oNIZx9IhE5WOufwwWkYEQotUhJ1YRXdVYFd9lcE7XfROUSPNMpsArWfUE4CeTr20K9qfzZfMV1RCqVtDt6xueXFb3xVdcEC4+OZX1RgWDEEnxUwQYqtrEv075AJIvlugeYk+KTzhte7mZzcudtgzkVsgg/dDPklQcidxLidTKV/fXgX5k6gPKB9tjTE7bMQSwyb5SPKzwqM1YqOpjTbwvmfSxmznl8W4vGo3zevvw9Chz2uzxHaG26085mBj49zsXwL9ZkbYhYMS5DaAVEJ3glyCkhfQ6mEQ+OAUFgQpWXBwJ7HbpmlRe88+PWUOTRj/WL12ZUltPm0PxtUMTMII1T4dD6go2l37nemNmgyeu4+mMbd4eZIm50JEDccjPsRNGE+Ubx3Vk9jDi2O2qU/2+Z8DITiYWbST6EjqlEchS+jiI4AI6uW0FiyEjqhIbjcoy3UK0sj7qNStRSMDIv0psQiWZWokv2tpbMxcWGHAX+OAps43aPUwciwkbsq0S2bCj3RFWdvny2Lt45UMYXFrZj++QZT5+539hfw4gCLXt9fF3gp8+x3Rz6jc4qKBIpBnTgQ0E+2JCTvJjOcEiIix82StewAU0UjhnC7pW5+WsmJIi2snL2izfPJckAphlfc1XDDd4nXb7Stb/cc4/Cgx8f4czOIluF+bU/mSwZj3Gu65gZUY7elQbaK+6hr8H055IwoYSi2FTXRpn05f7e8UWn38TwxNBg/flyC25evAowDA0OPjj4Bq7p2eCsC20l31Jf52rMcCk6x/VylmUJSK5/r/FkoN55rHG3dv7vFZa9YHxQgywDbYn1rYvljS68Tg+dwr6V6snqIRvr4ePmaxECSNkw4Kydu0Be4ifXrkGEyu7wZr+9QwfC6T2Vl8X6lWTXSF+YGk6yd0lpIUB+0JkJ8qiST+szkfcPNPjJx2XIpwnZsNFNh4uAy4hM+vhhXBcPVvKpwgf639evWNfm7ZhtedJgdsYbilSfdkMPiPZNjs6bbpQadJvEkaq5cUp/20SQqQ+DU7RKDHDykXrjkm1lMUys+dVol6JugVfHpixKoMHKgGug1Pb0IDPfN7eU2gPPJyqEB5jFINNvgeF4gW3IJHqeX1UJoBTxNa+EoMzblS8YL5hiIxISm41cDvx/AlK0aDl3TBHnA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2024 17:54:48.6631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 426026ec-ba40-43c0-adeb-08dcfcf9c690 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7464 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v6: * Drop all static key stuff and just call in __switch_to when cpu feature enabled (Boris) --- arch/x86/kernel/process_32.c | 4 ++++ arch/x86/kernel/process_64.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 0917c7f25720b..0bb6391b9089b 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -213,6 +213,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70d..371e0e8f987fa 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; }