| Message ID | 20241114193632.110062-1-hdegoede@redhat.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | platform/x86: p2sb: Cache correct PCI bar for P2SB on Denverton and Gemini Lake | expand |
On Thu, Nov 14, 2024 at 9:36 PM Hans de Goede <hdegoede@redhat.com> wrote: > > Gemine Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and Gemini > as such has the P2SB at device.function 13.0, rather then at the default > 31.1, just like Apollo Lake. > > At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus, > so that the correct PCI bar gets cached. > > This fixes P2SB unhiding not working on these devices, which fixes > SPI support for the bootrom SPI controller not working. Reviewed-by: Andy Shevchenko <andy@kernel.org> -- With Best Regards, Andy Shevchenko
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c index 31f38309b389..d51eb0db0626 100644 --- a/drivers/platform/x86/p2sb.c +++ b/drivers/platform/x86/p2sb.c @@ -25,6 +25,7 @@ static const struct x86_cpu_id p2sb_cpu_ids[] = { X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, P2SB_DEVFN_GOLDMONT), {} };
Gemine Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and as such has the P2SB at device.function 13.0, rather then at the default 31.1, just like Apollo Lake. At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus, so that the correct PCI bar gets cached. This fixes P2SB unhiding not working on these devices, which fixes SPI support for the bootrom SPI controller not working. Fixes: 2841631a0365 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe") Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- drivers/platform/x86/p2sb.c | 1 + 1 file changed, 1 insertion(+)