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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009D.mail.protection.outlook.com (10.167.244.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:45:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:37 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:34 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 05/10] platform/mellanox: mlxreg-hotplug: Add support for new flavor of capability registers Date: Mon, 13 Jan 2025 10:43:27 +0200 Message-ID: <20250113084337.24763-6-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|PH8PR12MB7448:EE_ X-MS-Office365-Filtering-Correlation-Id: ce10d5b5-42ea-4044-bae9-08dd33aeae1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:45:49.3269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce10d5b5-42ea-4044-bae9-08dd33aeae1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7448 Hotplug platform data is common across the various systems, while hotplug driver should be able to configure only the instances relevant to specific system. For example, platform hoptplug data might contain descriptions for fan1, fan2, ..., fan{n}, while some systems equipped with all 'n' fans, others with less. Same for power units, power controllers, ASICs and so on. For detection of the real number of equipped devices capability registers are used. These registers used to indicate presence of hotplug devices through the bitmap. For some new big modular systems, these registers will provide presence by counters. Use slot parameter to determine whether capability register contains bitmask or counter. Some 'capability' registers can be shared between different resources. Use fields 'capability_bit' and 'capability_mask' for getting only relevant capability bits. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlxreg-hotplug.c | 23 ++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index 0ce9fff1f7d4..3e480c322353 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -274,6 +274,13 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; + if (!regval) + continue; + + /* Remove non-relevant bits. */ + if (item->capability_mask) + regval = rol32(regval & item->capability_mask, + item->capability_bit); item->mask = GENMASK((regval & item->mask) - 1, 0); } @@ -294,7 +301,19 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; - if (!(regval & data->bit)) { + /* + * In case slot field is provided, capability + * register contains counter, otherwise bitmask. + * Skip non-relevant entries if slot set and + * exceeds counter. Othewise validate entry by + * matching bitmask. + */ + if (data->capability_mask) + regval = rol32(regval & data->capability_mask, + data->capability_bit); + if (data->slot > regval) { + break; + } else if (!(regval & data->bit) && !data->slot) { data++; continue; } @@ -611,7 +630,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) if (ret) goto out; - if (!(regval & data->bit)) + if (!(regval & data->bit) && !data->slot) item->mask &= ~BIT(j); } }