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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 08:00:10.3344 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5cee2357-7c4c-430a-a969-08dd3603ccce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8275 Some 'capability' registers can be shared between different resources. Add new fields 'capability_bit' and 'capability_mask' to structs 'mlxreg_core_data' and 'mlxreg_core_item' for getting only relevant capability bits. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- include/linux/platform_data/mlxreg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 0b9f81a6f753..d9f679752226 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -118,6 +118,8 @@ struct mlxreg_hotplug_device { * @mask: attribute access mask; * @bit: attribute effective bit; * @capability: attribute capability register; + * @capability_bit: started bit in attribute capability register; + * @capability_mask: mask in attribute capability register; * @reg_prsnt: attribute presence register; * @reg_sync: attribute synch register; * @reg_pwr: attribute power register; @@ -138,6 +140,8 @@ struct mlxreg_core_data { u32 mask; u32 bit; u32 capability; + u32 capability_bit; + u32 capability_mask; u32 reg_prsnt; u32 reg_sync; u32 reg_pwr; @@ -162,6 +166,8 @@ struct mlxreg_core_data { * @reg: group interrupt status register; * @mask: group interrupt mask; * @capability: group capability register; + * @capability_bit: started bit in attribute capability register; + * @capability_mask: mask in attribute capability register; * @cache: last status value for elements fro the same group; * @count: number of available elements in the group; * @ind: element's index inside the group; @@ -175,6 +181,8 @@ struct mlxreg_core_item { u32 reg; u32 mask; u32 capability; + u32 capability_bit; + u32 capability_mask; u32 cache; u8 count; u8 ind;