From patchwork Tue Feb 18 19:08:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980618 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2646271294; Tue, 18 Feb 2025 19:08:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905736; cv=none; b=t2aunY5Q9UUFHwI14AVx6y6RsSHyujSvKhtjSEOZdV1JWzQdwS4E8oediUcEyqPsVwVjJjERZ6jegm9LcVdxiWCycFnG6MHozsoea6WieNfS80DP6zQO1V/LcSif7YljvlzJ1bwDFu7ndHflltDCYlI5AH6i5shWG3xfC7d+HGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905736; c=relaxed/simple; bh=rLFz3Ld5AzSqmno+C7ltDttN21W0DB+vJuD4uskXVzM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DrKLcXkqyL76ETP7sWC+2hGsN4eCccitBfjA3v8kZDMFZKyy7uIvDaec553eF7i0+dOHDdMehZZY8Ujt1qdDiB9xNBAScALowG735Bir6kJf4g4PZHNqGLbRkop8VnbUuA7BDVhPYUodxKgblRFQISx25gez7oLPJjF4D7VCiCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z1muFOCi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z1muFOCi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63982C4CEE2; Tue, 18 Feb 2025 19:08:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905736; bh=rLFz3Ld5AzSqmno+C7ltDttN21W0DB+vJuD4uskXVzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z1muFOCiAfjE2G5d5vhAVWYaoK2Zcjx+oIKI3TeRx859dFRE06AHciLOjP8y8IE7q G2kaybqdgi87AABycGCMsLhy2sVa6hWtfIJHd/tWNsT97TG8PLl3WX/B3UVxnPHhoX XPAs3o0M3Q0FJZLOOiFWbtWn8rYAZXPlM2jAPMHmCfcYu9FQJNkhHDqO6dbf/6PBG0 svBuVZIpIIxVkeggvFLPLMZsOOQodiYMap9azVWADdmkbuV9EfwSaWig1c3FiIRBFv /Rh4wkWAkvjLDbiIGmrlVVGlXlp+Qoa1NLvx9yv7pgTpRbUhDSXr3nwhudWvBwbrxz rDg8SQhP9jSaQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Tue, 18 Feb 2025 13:08:12 -0600 Message-ID: <20250218190822.1039982-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 72765b2fe0d87..c84930610c7e6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -716,6 +716,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e