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Wed, 17 Apr 2024 00:30:35 -0700 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v1 3/3] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Date: Wed, 17 Apr 2024 03:30:18 -0400 Message-ID: <433fac1cffd9128a10eb2eff85b11ff671c9962f.1713334019.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|IA1PR12MB8190:EE_ X-MS-Office365-Filtering-Correlation-Id: d10587c7-e00c-4726-a5b3-08dc5eb04ded X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IOIZZqPIvp62lWYZH+XfxPWiU7PXmAyxHt8hneLwG9TJG7ivqCWtbZul8ZiLwWhj6mLU2mxC0DrYg1/9hpyCwyv7kyjFjQWs5ATOr8VuQncgrDmiYxC90UKmdWo19x+4ZwbdYj4pQuP5CBuF7vWL/kFDEL26YFKb0Z03LxZDTWXri+A5I7ElxgEesDkifi4AZUaewcVmmQ/CkKwBa5Erjin/mDh3XUmESO9pFEoPXsvuwHZVsmaiC/aUZXAesTVGu40iK1fIL8m8uxRzMwg7Zlh7SPOVAWQHmkznsvFR3j2p0ExoN2QrqQ3cNPuwvy36rc7bTKIOPM1YrolQDj5Ahhgrk/MMMvYllfA2wFV1PwTF73Kng29GoRetqRkBNmpSThm4C0ZvQUBKj8KhBwTIcDpgC3xKhzQLAK9YNspgaDCvOHjnV2ez0xoSkfiPe5hdA1qxlcwt6bvjdY1qRCvDHrB2aVknkWuyAPK9DCi30jao97xX+YX3mXUfS3RCWVP8FN44FLKw2MyIlxKRzE4u9dkmLOqS4Zyj6y/BFW2sZv8mPFQ6H0/W8FUFQwFOUgrYC2lXIdorkHVJL/FK/jxhNqQJ3FMCDkmL6whpeQiqAT87wyUAUPdh4HYrA/hIZ15A8jFo6z4NGO2vpPc/g2eq+tVC1n9ErHHJ1Iii25tpYb4nYv8wr2DsFIZXAHuLhPy1mRy/+2U5/8rLn2CqWOCShwaJwaTIi21XUu1qRu8fpMP3wWpkHQF2PNXgsNcHlweU X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2024 07:30:49.3036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d10587c7-e00c-4726-a5b3-08dc5eb04ded X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8190 The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index 635ecc3b3845..1212a96fb3eb 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; /* UUID used to probe ATF service. */ @@ -1038,6 +1069,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size } else if (strstr(blk, "llt")) { events = mlxbf_pmc_llt_events; size = ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events = mlxbf_pmc_clock_events; + size = ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events = NULL; size = 0; @@ -1472,14 +1506,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) { - u32 ecc_out; + u32 reg; - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; - *result = ecc_out; + *result = reg; return 0; } @@ -1493,6 +1528,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; + if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, MLXBF_PMC_WRITE_REG_32, data);