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Thu, 9 Jan 2025 06:39:37 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v4 3/4] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Date: Thu, 9 Jan 2025 09:39:22 -0500 Message-ID: <6ea0699497479dfde0a52fcb28aef55aee1bbc0b.1736413033.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|SN7PR12MB6838:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a782d13-f0d8-40d3-9c63-08dd30bb7d46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: 0NEvQjWLJX0hSeHMM3aPEUdzTjQo7dGM+fyKRG87z4FlzbsheRk4lnVKfpEMM15Gz6IUxVFYWErVeJENuCEmNDt6kYsIylvZ8dwUqFay6wBuZLtxTU0CunmB6x709s60Lnw0VlsHgdBFIano4O5BvsIXd9n6f1TLHIB1fFBSQHwdd/JuOlW3mc8n9mRkf6OYj7jXngkZE5FimnXqpjFB1nPjPR5/muCGwxg8K11UpPY9dYkMujofsSKPByKLevYVfyof1Gt6LAbaBKeboIsvxNm5MnKB5f5v8/TijTGgFw4PRPzhiSAcDI3G6MOKJncECLe04hMN5ygUt4SqjDbFSeRFvwv8FcoWJfuX18zHdijiq8eaU6hb4Ua4FwCTgtp/x8+fPgl0U989s/dYpDk9PsrJseUBTgozk76TErIbsDKHR8Ns8wHF5xo6RrUprl028nJI9ShDmnPBoKzKgEJRFEhZbUy2gz4elA8yyX8KRFVLYV35y+gJObUS2eV8uxx7HZaCb6Thi6Iz9tPf42XMGe8P4gl4gKvbScxN7jdFMBaUdcBuwS0yka1/ANga5lPo258mBIrpplSE9/zdh7na+x37Yl5XlfbpkjATqsiJsnwE//z3x5OjxUzsIU33CBQ53PZqLI09tvh8EyExjWahdCTaDEmR+vhJHctmnc2kB3MZeSf7HDOuX/002jdMt+E+ZLtN1HiiLaGIxFsze1z1gaCOtQZXcWDgjs+Rf8TDEzd7u8fMK35czKEPN3ouE1pzU7DMyrVPaVem7GOC30D+dbVznc2bos36wlSHXN3h3xwaOSPNyO3JPlA5xPtFgkbPNDeYeuZCVq0c8x30tAF8u3RZXkx+9KmpHW1esqWg/lLjDhGbDFlSl5qpvYg/9g+lKOR9FVAiERuy1/i4GGeHH/vAKG03y+JU2+ebrWyMka/Pd58Z13OAbIUbeGr7LTTnwD/vDJBcTwmkve+fcA3F7mQBLWQcMtO2hcPCAxPIHczMoILnbZKNGIshU0//1mYXDAd11aWiwU59EKuMKmkCsdg/0puxN3On+fFgh2pW4UEYUw8TWLnQjd2RgoUTTfTPCpSpBuBwhYcwmMlW/lFHm7hrbLrvAHiHlnWjTaSUG1lECEjZh5ozxl8oErfprxvXORZsydE5BkXPTECYnStq3u72ISJVZm46YgiGARIReCvg50gv0hkUZd+liiOzFIZFyP18q2a474Peihgot3Mu1N1vMXWLnQtjyXV361AnSgCVnxvICrlPH5vZeyYHaPnrTKvtwAW9t/mROF3Rs5rpCxvoLgJJyNHE9cARARRk3EyO97NZZFwRD2houVVZWfFHOcgaoj+BwBIovBqXifjpnGPNWN0QDpruGbhVTn3YrLTZRbeI2yIeYVZMcsPrkXdMmIT/DDW3Si+ZEki8IgZvjIL8C0E+mNDa3pwpieqvOOQ7Y7qYtdquEqzK2GcBg/UfG3kctZOJa7Fj1ruSEIJi5ji9uqlJNBsdPJU7sP55rUI= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2025 14:39:57.3869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a782d13-f0d8-40d3-9c63-08dd30bb7d46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6838 The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index ce967030d62a..25270a425ded 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -862,6 +862,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; /* UUID used to probe ATF service. */ @@ -1035,6 +1066,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size } else if (strstr(blk, "llt")) { events = mlxbf_pmc_llt_events; size = ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events = mlxbf_pmc_clock_events; + size = ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events = NULL; size = 0; @@ -1469,14 +1503,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) { - u32 ecc_out; + u32 reg; - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; - *result = ecc_out; + *result = reg; return 0; } @@ -1490,6 +1525,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; + if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, MLXBF_PMC_WRITE_REG_32, data);