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Fri, 7 Jun 2024 03:21:23 -0700 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v3 3/4] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Date: Fri, 7 Jun 2024 06:21:13 -0400 Message-ID: <7f90c24049918ba877d6c576cfe995707d052bb9.1717755404.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|IA0PR12MB7749:EE_ X-MS-Office365-Filtering-Correlation-Id: 8db6d8e9-f077-4ed8-3f29-08dc86db9e3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|376005|36860700004|1800799015; X-Microsoft-Antispam-Message-Info: U+PyqktZZ+Cq/w3vs6VKHnnJ2e0TkwqjWmkOEllGEfWy+R5eo+4DJ/VuU2wZ7OmMm4Cu5rdDUxxwvPRPSItE6yCcrzil4XDPjlkcgCvJUdEGo0gr0laDbHCnloWokd6K2NWY7HfvTEfKcm60YbGNqwlr97O1lODSRCUfU1PBNiEnD6/V5DtJPDi8UGVYL9NeXonUS22KPHUcVxZ6oStAvvOYlPimh7uU7j2u7ByQJ3Gw/K2L8L+yRTQJyj5Q2VyJFPR+ELH7DpmVhcZR653U0+t2dy8ySktlhCCkryLBhclXRFHBj56MB04btdzjxU/FK8keeKG2/+/U3tj8NoJkEof4G8cFs0cKZ1XW40qaV9oiEfDULnKzmjIMZEThrC0p8Bu/5HIXHqpiuY8HwD2IFMSkQCHF3o9n56BmVRJEPidPKV/NMSg4KzPHbXwXv9KU75vYcBtEzQCNBWFTgd8sgTlmrS9hwyIWgX0Mx4pqSGs0IEavJoJC1EOLVYQDdQoGRMlf3QoAFj/AVWDRx9OfamCtkYSn1fcJEhZ0oKrJAEHguLKEp59BYG6QN8bxvUPVckjd/jjED1kFKj5ips3gNufK0XvnykMYfbqjg2sVRSesvUZdRiSMPCD5+PvlpFzAqhsTzMNvCFgDQYLSw8EDwiFkMwqvXkHcRSHKJWBNIvX/6Ut1CNhlt+lE6xzWgYe2dJ74Xy/hINt7N9TmpP/XNNxh4M3PGdcnNupKvJI9wI8zrJu4rEpc971CG5mgQhNtRMVpi7XeCdGDlpPZx9hRBOTGjtV3nVgGT9+nRk+0lscoFzRiG5Dmhw6N56i8pqF77d5HiHX8Q5Ea/z94ivyJfwZwLvkv14Dh8vfw2ecGY4E46c8jWHDc75NL8LIX49sF+xdtImeI1YCd4DjbRV2q1diZtlIBo7U+6L6VRjTCTPhVsXVKD/TlegITZcz19rx0sc+TeHhCB5B+mDqJPwUabh2ncHoMnY2Nez62W8e2LHjD2GthcglQCLuMopahPWjrzjhjMIX7rB/6NsfFsgzZtJH+oIwqtLpnTKf+QEtE4oPaDEdIN9jfVIuHgQliYY7YfoXdd8AEPPtycsJhTrZPp1KOvBaiSPehZGjSDYsKIdqnwwTxYiTes08l3fnjYxbm1/HCpTATwKn1SYkYvsMPB7y49fufwny2h+C9m3kR2qoFqaSVTs4BKZvJZ2vIA6TH90DUr7/lv//nJhfZadOA/Ti2g/zXukuhGDJq7nCHjZW4+g5fkQddv0WCURiJCyWytCXE7dQF1Xnzd8PEkmQzKgeVMPUaVHQd5rPA9RVF+FAY2cqBtnr50Ln3STFwUMguXLKDswq5FmJasRp1/gmUW4WDY33+yizDvOrEf1LbH7dTRbl9ehWOq+iQWtV2ahRv/PwPg7k3bZ4cOwkersXd1w== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(376005)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 10:21:39.0163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8db6d8e9-f077-4ed8-3f29-08dc86db9e3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7749 The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index 635ecc3b3845..1212a96fb3eb 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; /* UUID used to probe ATF service. */ @@ -1038,6 +1069,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size } else if (strstr(blk, "llt")) { events = mlxbf_pmc_llt_events; size = ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events = mlxbf_pmc_clock_events; + size = ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events = NULL; size = 0; @@ -1472,14 +1506,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) { - u32 ecc_out; + u32 reg; - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; - *result = ecc_out; + *result = reg; return 0; } @@ -1493,6 +1528,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; + if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, MLXBF_PMC_WRITE_REG_32, data);