From patchwork Thu Nov 14 17:01:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 11244037 X-Patchwork-Delegate: andy.shevchenko@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09D4D6C1 for ; Thu, 14 Nov 2019 17:01:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E897C2070E for ; Thu, 14 Nov 2019 17:01:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727126AbfKNRBt (ORCPT ); Thu, 14 Nov 2019 12:01:49 -0500 Received: from mga04.intel.com ([192.55.52.120]:50118 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727116AbfKNRBh (ORCPT ); Thu, 14 Nov 2019 12:01:37 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2019 09:01:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,304,1569308400"; d="scan'208";a="257506347" Received: from unknown (HELO gayuk-dev-mach.sc.intel.com) ([10.3.79.161]) by FMSMGA003.fm.intel.com with ESMTP; 14 Nov 2019 09:01:35 -0800 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: vishwanath.somayaji@intel.com, dvhart@infradead.org, linux-kernel@vger.kernel.org, charles.d.prestopine@intel.com, Gayatri Kammela , Peter Zijlstra , Srinivas Pandruvada , Andy Shevchenko , Kan Liang , "David E . Box" , Rajneesh Bhardwaj , Tony Luck Subject: [PATCH v3 6/7] platform/x86: Add Atom based Elkhart Lake (EHL) platform support to intel_pmc_core driver Date: Thu, 14 Nov 2019 09:01:19 -0800 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Add Elkhart Lake to the list of the platforms that intel_pmc_core driver supports for pmc_core device. Just like Ice Lake and Tiger Lake, Elkhart Lake can also reuse all the Cannon Lake PCH IPs. Also, it uses the same PCH IPs of Tiger Lake, no additional effort is needed to enable but to simply reuse them. Cc: Peter Zijlstra Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel_pmc_core.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index b708c04db752..94081710e0de 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -190,7 +190,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"SDX", BIT(4)}, {"SPE", BIT(5)}, {"Fuse", BIT(6)}, - /* Reserved for Cannon Lake but valid for Ice Lake and Tiger Lake */ + /* + * Reserved for Cannon Lake but valid for Ice Lake, + * Tiger Lake and Elkhart Lake. + */ {"SBR8", BIT(7)}, {"CSME_FSC", BIT(0)}, @@ -234,7 +237,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"HDA_PGD4", BIT(2)}, {"HDA_PGD5", BIT(3)}, {"HDA_PGD6", BIT(4)}, - /* Reserved for Cannon Lake but valid for Ice Lake and Tiger Lake */ + /* + * Reserved for Cannon Lake but valid for Ice Lake, + * Tiger Lake and Elkhart Lake. + */ {"PSF6", BIT(5)}, {"PSF7", BIT(6)}, {"PSF8", BIT(7)}, @@ -266,7 +272,7 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = { }; static const struct pmc_bit_map tgl_pfear_map[] = { - /* Tiger Lake generation onwards only */ + /* Tiger Lake and Elkhart Lake generation onwards only */ {"PSF9", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -872,6 +878,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map), INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map), INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map), + INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map), {} };