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Thu, 9 Jan 2025 06:39:35 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v4 2/4] platform/mellanox: mlxbf-pmc: Add support for monitoring cycle count Date: Thu, 9 Jan 2025 09:39:21 -0500 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CB:EE_|LV3PR12MB9438:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f8d88fa-7e17-4331-6c6e-08dd30bb7832 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: ZIrIkydCNjY5oh/jNymyiQFDzB1bs2tk1aB6c+MsFmnA0Tz1ZuMgx9Dz08tBPSBULubs70gbZBnw9AMLaVtl1iBH8tXELFwiVef2pKl2VirBSPrOz4lFcsfgACyLxd3A1Yr5N1vNVMMryClCi8xMDucnG6TP9npeLFmBxk2O17HXLH3Kpd24aS4kegBMvk02/ZZzb4EbbCWAJtgCZdFDG3km1mmGJgFHwKX4feD+zIcowKV5VhQjX1KWWma12tS8cFaLLjALqKz4tTELWeAg9KcEiMCkWohD7EGspZKAwY+3eiILCRHCXUv7PgH4UI/a+FjLehZqdnNv/d8fqiWBpLn8WVfxeN/YZwwYYd5mihNYzySs1h3oRHEU+WES2FrOkrjw+IvAYAK7JDB+ml5HaIH+kFG9NA/TOZC/NmdHTLXeVZWigKG7Y1LednoyOGzxSWBJRGLv7bQtEs8H6SteMdXtsFrfLhwtPdFhc0j4w7ohIZjmobccF3lYkBLuV2aG+3cdDoh7nB8eC5+NCMrEJzel9bBqACsVDeJ5bd8TJcCK0KhtT4TaDn1VPS+OLrvGmJ9Azt2txD7x3q+BcMdtjhBsJVpvJHIe8EzKn8GB2PS2hwN7YqXZD30dRTqsuLDWTBa2xpNPBMIxj36WdUwqcRUjKIVvTv+3YVXT7Y0zRj0tt1HcrXeRYOp8L+LRq0EGJbhCJhyNLmGLi2r19FoxUt4dzPDCp8VLolWYzUb7ZfkHyMZub4dePm2mWC9ZiCliguZvo+rAGMC2hbpQENCC97AFS9Giwl/swyWuocWC0gO6osrcQCeGl7xwnHKF5zLiO3eNwpY65FsWaLCsJLtWd/q8mtv5Ii+NPcMtuApH2yoJU5E2qHqpC0qHscjcgg1gnYzxmvtqqGBPDLCELckncpSu5XMFZyq9qThlliHEwiDH2m39uEM4l/0/GotwbNXbeBeJndd1/ONV9YhxB7zWZ3rJmK0COayIbuQKezL7g5z9FUimyrPipPhHJwAtBmoBnxd95IR1mdCRoiTOkku+IZ4gbuC8GLNl1Zf/0j+V0vE0qHENMBjFM2e2cAGpnFCpk3V1/iUeUcmOpoqn/Mhv8glF9Qp5ydKcbKUJD7i+Cpuxd5zicvisRLQi9sHxeHrkxlRkd7Vyi6FyTQ/Idy/+j9x+cbXpNKfH5CdFfkJmf8kXtC4VBJTFpH50oeQ6dxDymAU0ZEOi3KDvKgJ7Kjg8yMaarAiCMmMD3CvcpQrHRKeTUxZOGK6GMz/YGmMg8p7RUjv6O8Ly+6VSuvD/m6RQrILSujP1JuqLPbt/nqSDLqSa0+pdm0hDX7mITAHUSS9AXNPp+iGnuI+mJHMdOQMcOZ0tqAUmve9Qmbe63jLhFsMDzmgL/fQZBoG6cRIklFDa84ZvkgAJT30FsaBZUuvdiP+42MEIted7EAffeI5K+NxHH/DiQOGpKpAJfzSZf+iJZ3kZfSjow7Gyj6V9uJhrk2vF79FjccSEZJiu5oFUoao= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2025 14:39:48.9754 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f8d88fa-7e17-4331-6c6e-08dd30bb7832 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9438 Add support for programming any counter to monitor the cycle count. This will allow the user to repurpose and dedicate any of the counters in the block to counting cycles. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index 9d18dfca6a67..ce967030d62a 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -88,6 +88,7 @@ #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ) #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4) #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc) /** @@ -114,6 +115,7 @@ struct mlxbf_pmc_attribute { * @attr_event: Attributes for "event" sysfs files * @attr_event_list: Attributes for "event_list" sysfs files * @attr_enable: Attributes for "enable" sysfs files + * @attr_count_clock: Attributes for "count_clock" sysfs files * @block_attr: All attributes needed for the block * @block_attr_grp: Attribute group for the block */ @@ -126,6 +128,7 @@ struct mlxbf_pmc_block_info { struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; struct mlxbf_pmc_attribute attr_enable; + struct mlxbf_pmc_attribute attr_count_clock; struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; struct attribute_group block_attr_grp; }; @@ -1763,6 +1766,49 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev, return count; } +/* Show function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + + blk_num = attr_count_clock->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", reg); +} + +/* Store function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + int err; + + blk_num = attr_count_clock->nr; + + err = kstrtouint(buf, 0, ®); + if (err < 0) + return err; + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + /* Populate attributes for blocks with counters to monitor performance */ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_num) { @@ -1801,6 +1847,21 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_ attr = NULL; } + if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) { + /* Program crspace counters to count clock cycles using "count_clock" sysfs */ + attr = &pmc->block[blk_num].attr_count_clock; + attr->dev_attr.attr.mode = 0644; + attr->dev_attr.show = mlxbf_pmc_count_clock_show; + attr->dev_attr.store = mlxbf_pmc_count_clock_store; + attr->nr = blk_num; + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, + "count_clock"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; + attr = NULL; + } + pmc->block[blk_num].attr_counter = devm_kcalloc( dev, pmc->block[blk_num].counters, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);