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Mon, 29 Oct 2018 12:25:35 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 12:25:08 +0100 Message-Id: <1540812328-16163-1-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 00/20] target/mips: Add limited support for Ingenic's MXU ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Aleksandar Markovic This patch set begins to add MXU ASE instruction support. v7->v8: - corrected several mistakes in MXU ASE overview note - add several clarifying comments - rebased to the latest code v6->v7: - move MXU_EN check to the main MXU decoding function - amend MXU ASE overview note v5->v6: - added bit definitions for 'aptn1' and 'eptn2'. - pool04 eliminated, since it is covered by a single instruction. - moved MUL, S32M2I, S32I2M handling out of main MXU switch. - rebased to the latest code (this series applies on top of the current MIPS pull request) v4->v5: - added full decoding engine for MXU ASE - changes on aptn2, optn2, optn3 are now stand-alone patches - all patches on individual instructions are reworked to fit new decoding engine, and also cosmetically improved - rebased to the latest code Aleksandar Markovic (8): target/mips: Amend MXU instruction opcodes target/mips: Add and integrate MXU decoding engine placeholder target/mips: Add MXU decoding engine target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch target/mips: Move MXU_EN check one level higher target/mips: Amend MXU ASE overview note Craig Janeczek (12): target/mips: Introduce MXU registers target/mips: Define a bit for MXU in insn_flags target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' target/mips: Add bit encoding for MXU operand getting pattern 'optn2' target/mips: Add bit encoding for MXU operand getting pattern 'optn3' target/mips: Add emulation of non-MXU MULL within MXU decoding engine target/mips: Add emulation of MXU instructions S32I2M and S32M2I target/mips: Add emulation of MXU instruction S8LDD target/mips: Add emulation of MXU instruction D16MUL target/mips: Add emulation of MXU instruction D16MAC target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU target/mips: Add emulation of MXU instructions S32LDD and S32LDDR target/mips/cpu.h | 10 + target/mips/mips-defs.h | 1 + target/mips/translate.c | 2104 ++++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 1896 insertions(+), 219 deletions(-)