From patchwork Sat Jul 4 11:36:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Liu X-Patchwork-Id: 11643483 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BEF5618 for ; Sat, 4 Jul 2020 11:31:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A57D20885 for ; Sat, 4 Jul 2020 11:31:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A57D20885 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrgOL-0002CC-Ch for patchwork-qemu-devel@patchwork.kernel.org; Sat, 04 Jul 2020 07:31:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrgNC-0000Mg-18 for qemu-devel@nongnu.org; Sat, 04 Jul 2020 07:30:22 -0400 Received: from mga05.intel.com ([192.55.52.43]:24793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrgN9-0004K6-3v for qemu-devel@nongnu.org; Sat, 04 Jul 2020 07:30:21 -0400 IronPort-SDR: PvZxVWy1oCNs5MMvi8Fx72aGY9BZhet+fC5nJYoXsAUJCJe2zMGNqr4nXyn/F8TRrK2jn30mBg sSFfI5CJFBIA== X-IronPort-AV: E=McAfee;i="6000,8403,9671"; a="232105512" X-IronPort-AV: E=Sophos;i="5.75,311,1589266800"; d="scan'208";a="232105512" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2020 04:30:13 -0700 IronPort-SDR: GSHqnVmRDiPtAdZSC5vZa/h2yC5eU2cH4b7oY9vytCalTqCyF8rg8aCvYV1Gh3olTuAcyAsLut jluTzxSu4dRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,311,1589266800"; d="scan'208";a="266146751" Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by fmsmga007.fm.intel.com with ESMTP; 04 Jul 2020 04:30:13 -0700 From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [RFC v7 00/25] intel_iommu: expose Shared Virtual Addressing to VMs Date: Sat, 4 Jul 2020 04:36:24 -0700 Message-Id: <1593862609-36135-1-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 Received-SPF: pass client-ip=192.55.52.43; envelope-from=yi.l.liu@intel.com; helo=mga05.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/04 07:30:14 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, kevin.tian@intel.com, yi.l.liu@intel.com, kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, pbonzini@redhat.com, hao.wu@intel.com, jasowang@redhat.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Shared Virtual Addressing (SVA), a.k.a, Shared Virtual Memory (SVM) on Intel platforms allows address space sharing between device DMA and applications. SVA can reduce programming complexity and enhance security. This QEMU series is intended to expose SVA usage to VMs. i.e. Sharing guest application address space with passthru devices. This is called vSVA in this series. The whole vSVA enabling requires QEMU/VFIO/IOMMU changes. The high-level architecture for SVA virtualization is as below, the key design of vSVA support is to utilize the dual-stage IOMMU translation ( also known as IOMMU nesting translation) capability in host IOMMU. .-------------. .---------------------------. | vIOMMU | | Guest process CR3, FL only| | | '---------------------------' .----------------/ | PASID Entry |--- PASID cache flush - '-------------' | | | V | | CR3 in GPA '-------------' Guest ------| Shadow |--------------------------|-------- v v v Host .-------------. .----------------------. | pIOMMU | | Bind FL for GVA-GPA | | | '----------------------' .----------------/ | | PASID Entry | V (Nested xlate) '----------------\.------------------------------. | | |SL for GPA-HPA, default domain| | | '------------------------------' '-------------' Where: - FL = First level/stage one page tables - SL = Second level/stage two page tables The complete vSVA kernel upstream patches are divided into three phases: 1. Common APIs and PCI device direct assignment 2. IOMMU-backed Mediated Device assignment 3. Page Request Services (PRS) support This QEMU patchset is aiming for the phase 1 and phase 2. It is based on the kernel series below: [PATCH v4 00/15] vfio: expose virtual Shared Virtual Addressing to VMs https://lore.kernel.org/kvm/1593861989-35920-1-git-send-email-yi.l.liu@intel.com/ Patch Overview: 1. patch 0001 - 0002: update kernel header files 2. patch 0003 - 0007: select VFIO_TYPE1_NESTING_IOMMU for vIOMMU built on IOMMU nesting translation. 3. patch 0008 - 0010: set HostIOMMUContext to vIOMMU. 4. patch 0011 - 0013: allocate PASID for vIOMMU. 5. patch 0014 - 0015: PASID cache management for Intel vIOMMU. 6. patch 0016 - 0020: bind guest page table to host. 7. patch 0021 - 0024: flush first level/stage cache for vIOMMU. 8. patch 0025: expose SVA to VM by x-scalable-mode="modern" The complete QEMU set can be found in below link: https://github.com/luxis1999/qemu.git: vsva_5.8_rc3_qemu_rfcv7 Complete kernel can be found in: https://github.com/luxis1999/linux-vsva.git: vsva-linux-5.8-rc3-v4 Tests: basci vSVA functionality test, VM reboot/shutdown/crash, kernel build in guest, boot VM with vSVA disabled, full comapilation with all archs, passthru entire PCI device, passthru Scalable IOV ADI. Regards, Yi Liu Changelog: - RFC v6 -> RFC v7: a) Rebase to latest kernel implementation (5.8-rc3 vsva) RFC v6: https://lore.kernel.org/kvm/1591880064-30638-1-git-send-email-yi.l.liu@intel.com/ - RFC v5 -> RFC v6: a) Use RFC instead of formal patch as kernel patch is in progress. b) Address comments from Peter and Eric. c) Add get_iommu_attr() to advertise vIOMMU nesting requirement to VFIO. d) Update per latest kernel UAPI definition. e) Add patch 0017 to check iommu nesting cap info in set_iommu(). RFC v5: https://www.spinics.net/lists/kvm/msg211475.html - RFC v4 -> RFC v5: a) Refactor the vfio HostIOMMUContext init code (patch 0008 - 0009 of v1 series) b) Refactor the pasid binding handling (patch 0011 - 0016 of v1 series) RFC v4: https://patchwork.ozlabs.org/cover/1259648/ - RFC v3.1 -> RFC v4: a) Implement HostIOMMUContext in QOM manner. b) Add pci_set/unset_iommu_context() to register HostIOMMUContext to vIOMMU, thus the lifecircle of HostIOMMUContext is awared in vIOMMU side. In such way, vIOMMU could use the methods provided by the HostIOMMUContext safely. c) Add back patch "[RFC v3 01/25] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps" RFCv3.1: https://patchwork.kernel.org/cover/11397879/ - RFC v3 -> v3.1: a) Drop IOMMUContext, and rename DualStageIOMMUObject to HostIOMMUContext. HostIOMMUContext is per-vfio-container, it is exposed to vIOMMU via PCI layer. VFIO registers a PCIHostIOMMUFunc callback to PCI layer, vIOMMU could get HostIOMMUContext instance via it. b) Check IOMMU uAPI version by VFIO_CHECK_EXTENSION c) Add a check on VFIO_PASID_REQ availability via VFIO_GET_IOMMU_IHNFO d) Reorder the series, put vSVA linux header file update in the beginning put the x-scalable-mode option mofification in the end of the series. e) Dropped patch "[RFC v3 01/25] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps" RFCv3: https://patchwork.kernel.org/cover/11356033/ - RFC v2 -> v3: a) Introduce DualStageIOMMUObject to abstract the host IOMMU programming capability. e.g. request PASID from host, setup IOMMU nesting translation on host IOMMU. The pasid_alloc/bind_guest_page_table/iommu_cache_flush operations are moved to be DualStageIOMMUOps. Thus, DualStageIOMMUObject is an abstract layer which provides QEMU vIOMMU emulators with an explicit method to program host IOMMU. b) Compared with RFC v2, the IOMMUContext has also been updated. It is modified to provide an abstract for vIOMMU emulators. It provides the method for pass-through modules (like VFIO) to communicate with host IOMMU. e.g. tell vIOMMU emulators about the IOMMU nesting capability on host side and report the host IOMMU DMA translation faults to vIOMMU emulators. RFC v2: https://www.spinics.net/lists/kvm/msg198556.html - RFC v1 -> v2: Introduce IOMMUContext to abstract the connection between VFIO and vIOMMU emulators, which is a replacement of the PCIPASIDOps in RFC v1. Modify x-scalable-mode to be string option instead of adding a new option as RFC v1 did. Refined the pasid cache management and addressed the TODOs mentioned in RFC v1. RFC v1: https://patchwork.kernel.org/cover/11033657/ --- Eric Auger (1): scripts/update-linux-headers: Import iommu.h Liu Yi L (24): header file update VFIO/IOMMU vSVA APIs kernel 5.8-rc3 hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps hw/pci: introduce pci_device_get_iommu_attr() intel_iommu: add get_iommu_attr() callback vfio: pass nesting requirement into vfio_get_group() vfio: check VFIO_TYPE1_NESTING_IOMMU support hw/iommu: introduce HostIOMMUContext hw/pci: introduce pci_device_set/unset_iommu_context() intel_iommu: add set/unset_iommu_context callback vfio/common: provide PASID alloc/free hooks vfio: init HostIOMMUContext per-container intel_iommu: add virtual command capability support intel_iommu: process PASID cache invalidation intel_iommu: add PASID cache management infrastructure vfio: add bind stage-1 page table support intel_iommu: sync IOMMU nesting cap info for assigned devices intel_iommu: bind/unbind guest page table to host intel_iommu: replay pasid binds after context cache invalidation intel_iommu: do not pass down pasid bind for PASID #0 vfio: add support for flush iommu stage-1 cache intel_iommu: process PASID-based iotlb invalidation intel_iommu: propagate PASID-based iotlb invalidation to host intel_iommu: process PASID-based Device-TLB invalidation intel_iommu: modify x-scalable-mode to be string option hw/Makefile.objs | 1 + hw/alpha/typhoon.c | 6 +- hw/arm/smmu-common.c | 6 +- hw/hppa/dino.c | 6 +- hw/i386/amd_iommu.c | 6 +- hw/i386/intel_iommu.c | 1231 ++++++++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 131 ++++ hw/i386/trace-events | 6 + hw/iommu/Makefile.objs | 1 + hw/iommu/host_iommu_context.c | 171 +++++ hw/pci-host/designware.c | 6 +- hw/pci-host/pnv_phb3.c | 6 +- hw/pci-host/pnv_phb4.c | 6 +- hw/pci-host/ppce500.c | 6 +- hw/pci-host/prep.c | 6 +- hw/pci-host/sabre.c | 6 +- hw/pci/pci.c | 73 +- hw/ppc/ppc440_pcix.c | 6 +- hw/ppc/spapr_pci.c | 6 +- hw/s390x/s390-pci-bus.c | 8 +- hw/vfio/ap.c | 2 +- hw/vfio/ccw.c | 2 +- hw/vfio/common.c | 297 +++++++- hw/vfio/pci.c | 26 +- hw/vfio/platform.c | 2 +- hw/virtio/virtio-iommu.c | 6 +- include/hw/i386/intel_iommu.h | 61 +- include/hw/iommu/host_iommu_context.h | 103 +++ include/hw/pci/pci.h | 25 +- include/hw/pci/pci_bus.h | 2 +- include/hw/vfio/vfio-common.h | 7 +- linux-headers/linux/iommu.h | 413 +++++++++++ linux-headers/linux/vfio.h | 87 ++- scripts/update-linux-headers.sh | 2 +- 34 files changed, 2668 insertions(+), 61 deletions(-) create mode 100644 hw/iommu/Makefile.objs create mode 100644 hw/iommu/host_iommu_context.c create mode 100644 include/hw/iommu/host_iommu_context.h create mode 100644 linux-headers/linux/iommu.h