From patchwork Thu Mar 25 07:22:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingang X-Patchwork-Id: 12163281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAF47C433DB for ; Thu, 25 Mar 2021 07:25:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3778E6196C for ; Thu, 25 Mar 2021 07:25:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3778E6196C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:55596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lPKMj-0006TF-6q for qemu-devel@archiver.kernel.org; Thu, 25 Mar 2021 03:25:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPKKu-0004NU-Eq; Thu, 25 Mar 2021 03:23:20 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPKKs-0002zM-5b; Thu, 25 Mar 2021 03:23:20 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4F5c3F16x1zrZjK; Thu, 25 Mar 2021 15:21:13 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.498.0; Thu, 25 Mar 2021 15:23:05 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC RESEND v2 0/6] Introduce IOMMU Option For PCI Root Bus Date: Thu, 25 Mar 2021 07:22:39 +0000 Message-ID: <1616656965-23328-1-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangxingang5@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xingang Wang These patches add support for configure iommu on/off for pci root bus, including primary bus and pxb root bus. At present, All root bus will go through iommu when iommu is configured, which is not flexible. So this add option to enable/disable iommu for primary bus and pxb root bus. When iommu is enabled for the root bus, devices attached to it will go through iommu. When iommu is disabled for the root bus, devices will not go through iommu accordingly. The option example for iommu configuration is like the following: primary root bus option: arm: -machine virt iommu=smmuv3,primary_bus_iommu=false(or true) x86: -machine q35,primary_bus_iommu=false(or true) pxb root bus: -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1,iommu=false History: v1 -> v2: - rebase on top of v6.0.0-rc0 - Fix some issues - Took into account Eric's comments, and remove the PCI_BUS_IOMMU flag, replace it with a property in PCIHostState. - Add support for x86 iommu option Xingang Wang (6): hw/pci/pci_host: Add iommu property for pci host hw/pci: Add iommu option for pci root bus hw/pci: Add pci_root_bus_max_bus hw/arm/virt-acpi-build: Add explicit idmap info in IORT table hw/i386/acpi-build: Add explicit scope in DMAR table hw/i386/acpi-build: Add iommu filter in IVRS table hw/arm/virt-acpi-build.c | 103 ++++++++++++++++++++++------ hw/arm/virt.c | 25 +++++++ hw/i386/acpi-build.c | 70 ++++++++++++++++++- hw/i386/pc.c | 19 +++++ hw/pci-bridge/pci_expander_bridge.c | 3 + hw/pci-host/q35.c | 1 + hw/pci/pci.c | 52 +++++++++++++- hw/pci/pci_host.c | 2 + include/hw/arm/virt.h | 1 + include/hw/i386/pc.h | 1 + include/hw/pci/pci.h | 2 + include/hw/pci/pci_host.h | 1 + 12 files changed, 254 insertions(+), 26 deletions(-)