[qemu,v2,0/1] target/riscv: Add Zilsd and Zcmlsd extension support

Message

~liuxu July 12, 2024, 3:32 a.m. UTC

In this version of the patch:
1. Adjusted the code formatting issue
2. Optimize the processing of all instructions

lxx (1):
  target/riscv: Add Zilsd and Zcmlsd extension support

 target/riscv/cpu.c                         |  4 +
 target/riscv/cpu_cfg.h                     |  2 +
 target/riscv/insn16.decode                 |  8 ++
 target/riscv/insn32.decode                 | 12 ++-
 target/riscv/insn_trans/trans_zcmlsd.c.inc | 91 +++++++++++++++++++++
 target/riscv/insn_trans/trans_zilsd.c.inc  | 94 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                 | 13 +++
 target/riscv/translate.c                   |  2 +
 8 files changed, 224 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zcmlsd.c.inc
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc