[qemu,v4,0/1] target/riscv: Add Zilsd and Zclsd extension support

Message

~liuxu Aug. 16, 2024, 7:30 a.m. UTC

Last reply: https://lists.gnu.org/archive/html/qemu-
devel/2024-08/msg01631.html

This version no longer separates the implementation of Zilsd and Zclsd
extensions.

lxx (1):
  target/riscv: Add Zilsd and Zclsd extension support

 target/riscv/cpu.c                        |   4 +
 target/riscv/cpu_cfg.h                    |   2 +
 target/riscv/insn16.decode                |   8 ++
 target/riscv/insn32.decode                |  12 +-
 target/riscv/insn_trans/trans_zilsd.c.inc | 128 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                |  16 +++
 target/riscv/translate.c                  |   1 +
 7 files changed, 169 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc