From patchwork Wed Oct 10 20:37:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 10635227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4A2746E4 for ; Wed, 10 Oct 2018 20:40:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87E512AC84 for ; Wed, 10 Oct 2018 20:40:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7BA7F2ACAC; Wed, 10 Oct 2018 20:40:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 506302AC84 for ; Wed, 10 Oct 2018 20:40:06 +0000 (UTC) Received: from localhost ([::1]:59036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gALH3-000429-Gu for patchwork-qemu-devel@patchwork.kernel.org; Wed, 10 Oct 2018 16:40:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gALFT-0002nU-Sc for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gALFR-0002NO-BL for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:26 -0400 Received: from mail-yw1-xc43.google.com ([2607:f8b0:4864:20::c43]:34683) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gALFJ-0002J3-Ev; Wed, 10 Oct 2018 16:38:18 -0400 Received: by mail-yw1-xc43.google.com with SMTP id m129-v6so2730744ywc.1; Wed, 10 Oct 2018 13:38:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Gj1Wz3YTSMIBnewLGtsEovmWfmex6XgUSSKzzs6EYLI=; b=XCUEHesE34ATCmtapNB1v4JEDXDBOasRVTqhi0zmoGgdju86QvZFcqvxZ4DWUdkk3l Pn2N7uNuog5RMCH15L9YbHGmc5VpEz44wmW7RPPEsvgVRu+mnyuyQDMRlLYBXzxLNu5l sq7aduCulrsnOKBbEk0Sz1sUu/MNXp2w2FXnwGjdrPFPfcn/SQvPhBdODSEBe49oeiNp G7i/CxhwzZEvsnej/KDiRNx8DdrREdE4EMxVdN9wWEJGw6c9MKGhsvQ/IpXPTE2WozRK HtPLP3WIsJfh7pBRHvtkfDVf4+WjqT1xCKq4F0vaEpXOrG77AvlFtCUsPQN2PnA82Nae diBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Gj1Wz3YTSMIBnewLGtsEovmWfmex6XgUSSKzzs6EYLI=; b=HP6MMtg4WRAVpN6bjgImKKW2GA20dHIMSGayAsnHG9Y/YiQvAO30OSCVfSbkCRulW2 bLhFAnibmzo0vQVtALsoNGef6QFLQN2yHtRHQ0xtf/LRcnIWp2DDvu4Fr1JUMQdu/ByA c6ioQEyEc0fTcJS8GbReos5MTDrrtrLJmZNmqi1rtKYCILe+vlICPFR432bNdEcvptiN p5kLmrsk9bHU4dpza/r3QFKbNCnKuZZrl/9Or9cSShG0HB+DVHoNHOAmFLG0dYrUWJXr UAXGGZlCUSYeKHnSaQUlO1jdvukUKnJl4f6SQkxXNATKk+zQG2ytNdldILbbVlpj487S OHhw== X-Gm-Message-State: ABuFfoj4cJ4xFrdXHhLCEs5csqB6SM3xhni3xQvzIjBTwmacoXRQe0dS aWs0w6vNhH/B4c7uNkkXD2ue62S7 X-Google-Smtp-Source: ACcGV61VRxY955Yyleh17TeEWnEMT7EoHnYywFuZX62QXLSOZriRJKQBRHZfiyM+Bc1usiXqfnPEKg== X-Received: by 2002:a81:6657:: with SMTP id a84-v6mr19047852ywc.311.1539203894523; Wed, 10 Oct 2018 13:38:14 -0700 (PDT) Received: from quinoa.localdomain ([216.85.170.153]) by smtp.gmail.com with ESMTPSA id u131-v6sm15170728ywf.13.2018.10.10.13.38.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Oct 2018 13:38:13 -0700 (PDT) From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Wed, 10 Oct 2018 16:37:21 -0400 Message-Id: <20181010203735.27918-1-aclindsa@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 Subject: [Qemu-devel] [PATCH v6 00/14] More fully implement ARM PMUv3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events. Since v5 [1] I have: * Taken a first pass at addressing migration * Restructured the list of supported events, and ensured they're all initialized * Fixed aliasing for PMOVSSET * Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1 * Addressed a few non-code issues (comment style, patch staging, spelling, etc.) [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html Aaron Lindsay (14): target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO target/arm: Mask PMOVSR writes based on supported counters migration: Add post_save function to VMStateDescription target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET target/arm: Add array for supported PMU events, generate PMCEID[01] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Send interrupts on PMU counter overflow docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 10 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 68 +++- target/arm/cpu64.c | 2 - target/arm/helper.c | 781 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 19 + 8 files changed, 817 insertions(+), 101 deletions(-)