From patchwork Fri Oct 12 17:30:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10639003 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BCB0112B for ; Fri, 12 Oct 2018 17:34:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0C962C17F for ; Fri, 12 Oct 2018 17:34:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF0FF2C244; Fri, 12 Oct 2018 17:34:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7EAE62C2C7 for ; Fri, 12 Oct 2018 17:34:50 +0000 (UTC) Received: from localhost ([::1]:41894 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Kr-0004Gp-N6 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 12 Oct 2018 13:34:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1HO-0001cx-W4 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1HL-0008Qo-LL for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:37078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1HK-0008Ov-RV for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:11 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1gB1HH-0001Eo-4H; Fri, 12 Oct 2018 19:31:07 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 2934316-5; Fri, 12 Oct 2018 17:31:07 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1HG-0006OT-PN; Fri, 12 Oct 2018 19:31:07 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:19 +0200 Message-Id: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 00/28] target/riscv: Convert to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi, this patchset converts the RISC-V decoder to decodetree in three major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-14]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 15-17]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 17-28]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. the full tree can be found here: https://github.com/bkoppelmann/qemu/tree/riscv-dt Cheers, Bastian Bastian Koppelmann (28): targer/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RVXI load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Replace gen_branch() with trans_branch() target/riscv: Replace gen_load() with trans_load() target/riscv: Replace gen_store() with trans_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv: Replace gen_exception_illegal with return false target/riscv/Makefile.objs | 17 + target/riscv/insn16.decode | 126 ++ target/riscv/insn32.decode | 255 +++ .../riscv/insn_trans/trans_privileged.inc.c | 109 + target/riscv/insn_trans/trans_rva.inc.c | 274 +++ target/riscv/insn_trans/trans_rvc.inc.c | 339 ++++ target/riscv/insn_trans/trans_rvd.inc.c | 407 ++++ target/riscv/insn_trans/trans_rvf.inc.c | 396 ++++ target/riscv/insn_trans/trans_rvi.inc.c | 624 ++++++ target/riscv/insn_trans/trans_rvm.inc.c | 94 + target/riscv/translate.c | 1745 ++--------------- 11 files changed, 2827 insertions(+), 1559 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c --- 2.19.1