| Message ID | 20190102055743.5052-1-clg@kaod.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | spapr: introduce the 'dual' interrupt mode XICS/XIVE | expand |
On Wed, Jan 02, 2019 at 06:57:33AM +0100, Cédric Le Goater wrote: > Hello, > > This series adds a new sPAPR IRQ backend called 'dual' which supports > both interrupt mode, the XIVE native exploitation mode and the legacy > compatibility mode (XICS). > > The machine operates with the legacy mode by default and lets CAS > negotiate a new interrupt mode. If a new mode is selected, it is > activated after a machine reset to take into account the required > changes. These impact the device tree layout, the interrupt presenter > object and the exposed MMIO regions in the case of XIVE. > > The preliminary changes for this new IRQ backend are the introduction > of a second interrupt presenter object under the PowerPCCPU to support > XIVE. The qemu_irq array of each interrupt controller model is also > made common and moved under the machine. Ok, I've now applied all of this series to ppc-for-4.0. > > > GitHub trees available here : > > QEMU sPAPR: > > https://github.com/legoater/qemu/commits/xive-next > > QEMU PowerNV: > > https://github.com/legoater/qemu/commits/powernv-3.1 > > Linux/KVM: > > https://github.com/legoater/linux/commits/xive-4.20 > > OPAL: > > https://github.com/legoater/skiboot/commits/xive > > Best wishes for 2019 ! > > C. > > > > Cédric Le Goater (10): > spapr: modify the prototype of the cpu_intc_create() method > ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU > ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the > CPU > spapr/xive: simplify the sPAPR IRQ qirq method for XIVE > ppc: export the XICS and XIVE set_irq handlers > pnv/psi: move the ICSState qemu_irq array under the PSI device model > spapr: move the ICSState qemu_irq array under the machine > ppc/xics: allow ICSState to have an offset 0 > spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS > spapr: enable XIVE MMIOs at reset > > include/hw/ppc/pnv.h | 2 +- > include/hw/ppc/pnv_psi.h | 1 + > include/hw/ppc/spapr.h | 1 + > include/hw/ppc/spapr_irq.h | 6 +- > include/hw/ppc/spapr_xive.h | 2 +- > include/hw/ppc/xics.h | 6 +- > include/hw/ppc/xive.h | 9 +- > target/ppc/cpu.h | 5 +- > hw/intc/spapr_xive.c | 23 ++- > hw/intc/xics.c | 4 +- > hw/intc/xics_kvm.c | 3 +- > hw/intc/xics_spapr.c | 10 +- > hw/intc/xive.c | 11 +- > hw/ppc/pnv.c | 27 ++-- > hw/ppc/pnv_core.c | 4 +- > hw/ppc/pnv_psi.c | 7 +- > hw/ppc/spapr.c | 12 +- > hw/ppc/spapr_cpu_core.c | 9 +- > hw/ppc/spapr_hcall.c | 11 ++ > hw/ppc/spapr_irq.c | 270 ++++++++++++++++++++++++++++++++++-- > 20 files changed, 342 insertions(+), 81 deletions(-) >
On 1/7/19 5:48 AM, David Gibson wrote: > On Wed, Jan 02, 2019 at 06:57:33AM +0100, Cédric Le Goater wrote: >> Hello, >> >> This series adds a new sPAPR IRQ backend called 'dual' which supports >> both interrupt mode, the XIVE native exploitation mode and the legacy >> compatibility mode (XICS). >> >> The machine operates with the legacy mode by default and lets CAS >> negotiate a new interrupt mode. If a new mode is selected, it is >> activated after a machine reset to take into account the required >> changes. These impact the device tree layout, the interrupt presenter >> object and the exposed MMIO regions in the case of XIVE. >> >> The preliminary changes for this new IRQ backend are the introduction >> of a second interrupt presenter object under the PowerPCCPU to support >> XIVE. The qemu_irq array of each interrupt controller model is also >> made common and moved under the machine. > > Ok, I've now applied all of this series to ppc-for-4.0. Thanks, We should pursue with KVM XIVE support now. Shall I send the Linux KVM and the QEMU KVM patchsets in parallel ? I still have some work to be done on the QEMU PowerNV before resending. Thanks, C. > >> >> >> GitHub trees available here : >> >> QEMU sPAPR: >> >> https://github.com/legoater/qemu/commits/xive-next >> >> QEMU PowerNV: >> >> https://github.com/legoater/qemu/commits/powernv-3.1 >> >> Linux/KVM: >> >> https://github.com/legoater/linux/commits/xive-4.20 >> >> OPAL: >> >> https://github.com/legoater/skiboot/commits/xive >> >> Best wishes for 2019 ! >> >> C. >> >> >> >> Cédric Le Goater (10): >> spapr: modify the prototype of the cpu_intc_create() method >> ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU >> ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the >> CPU >> spapr/xive: simplify the sPAPR IRQ qirq method for XIVE >> ppc: export the XICS and XIVE set_irq handlers >> pnv/psi: move the ICSState qemu_irq array under the PSI device model >> spapr: move the ICSState qemu_irq array under the machine >> ppc/xics: allow ICSState to have an offset 0 >> spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS >> spapr: enable XIVE MMIOs at reset >> >> include/hw/ppc/pnv.h | 2 +- >> include/hw/ppc/pnv_psi.h | 1 + >> include/hw/ppc/spapr.h | 1 + >> include/hw/ppc/spapr_irq.h | 6 +- >> include/hw/ppc/spapr_xive.h | 2 +- >> include/hw/ppc/xics.h | 6 +- >> include/hw/ppc/xive.h | 9 +- >> target/ppc/cpu.h | 5 +- >> hw/intc/spapr_xive.c | 23 ++- >> hw/intc/xics.c | 4 +- >> hw/intc/xics_kvm.c | 3 +- >> hw/intc/xics_spapr.c | 10 +- >> hw/intc/xive.c | 11 +- >> hw/ppc/pnv.c | 27 ++-- >> hw/ppc/pnv_core.c | 4 +- >> hw/ppc/pnv_psi.c | 7 +- >> hw/ppc/spapr.c | 12 +- >> hw/ppc/spapr_cpu_core.c | 9 +- >> hw/ppc/spapr_hcall.c | 11 ++ >> hw/ppc/spapr_irq.c | 270 ++++++++++++++++++++++++++++++++++-- >> 20 files changed, 342 insertions(+), 81 deletions(-) >> >
Hello, This series adds a new sPAPR IRQ backend called 'dual' which supports both interrupt mode, the XIVE native exploitation mode and the legacy compatibility mode (XICS). The machine operates with the legacy mode by default and lets CAS negotiate a new interrupt mode. If a new mode is selected, it is activated after a machine reset to take into account the required changes. These impact the device tree layout, the interrupt presenter object and the exposed MMIO regions in the case of XIVE. The preliminary changes for this new IRQ backend are the introduction of a second interrupt presenter object under the PowerPCCPU to support XIVE. The qemu_irq array of each interrupt controller model is also made common and moved under the machine. GitHub trees available here : QEMU sPAPR: https://github.com/legoater/qemu/commits/xive-next QEMU PowerNV: https://github.com/legoater/qemu/commits/powernv-3.1 Linux/KVM: https://github.com/legoater/linux/commits/xive-4.20 OPAL: https://github.com/legoater/skiboot/commits/xive Best wishes for 2019 ! C. Cédric Le Goater (10): spapr: modify the prototype of the cpu_intc_create() method ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU spapr/xive: simplify the sPAPR IRQ qirq method for XIVE ppc: export the XICS and XIVE set_irq handlers pnv/psi: move the ICSState qemu_irq array under the PSI device model spapr: move the ICSState qemu_irq array under the machine ppc/xics: allow ICSState to have an offset 0 spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS spapr: enable XIVE MMIOs at reset include/hw/ppc/pnv.h | 2 +- include/hw/ppc/pnv_psi.h | 1 + include/hw/ppc/spapr.h | 1 + include/hw/ppc/spapr_irq.h | 6 +- include/hw/ppc/spapr_xive.h | 2 +- include/hw/ppc/xics.h | 6 +- include/hw/ppc/xive.h | 9 +- target/ppc/cpu.h | 5 +- hw/intc/spapr_xive.c | 23 ++- hw/intc/xics.c | 4 +- hw/intc/xics_kvm.c | 3 +- hw/intc/xics_spapr.c | 10 +- hw/intc/xive.c | 11 +- hw/ppc/pnv.c | 27 ++-- hw/ppc/pnv_core.c | 4 +- hw/ppc/pnv_psi.c | 7 +- hw/ppc/spapr.c | 12 +- hw/ppc/spapr_cpu_core.c | 9 +- hw/ppc/spapr_hcall.c | 11 ++ hw/ppc/spapr_irq.c | 270 ++++++++++++++++++++++++++++++++++-- 20 files changed, 342 insertions(+), 81 deletions(-)