From patchwork Tue Jan 22 09:28:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10775309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A109B1390 for ; Tue, 22 Jan 2019 10:16:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90C012A26E for ; Tue, 22 Jan 2019 10:16:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 83C4624151; Tue, 22 Jan 2019 10:16:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0A61C24151 for ; Tue, 22 Jan 2019 10:16:51 +0000 (UTC) Received: from localhost ([127.0.0.1]:42201 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glt6w-0004PE-8Z for patchwork-qemu-devel@patchwork.kernel.org; Tue, 22 Jan 2019 05:16:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59386) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVs-0006Mz-Ie for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNS-0004c3-Dw for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:52 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41854) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNQ-0004Zj-By; Tue, 22 Jan 2019 04:29:50 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1glsNK-0004HT-GX; Tue, 22 Jan 2019 10:29:42 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100910-5; Tue, 22 Jan 2019 09:29:40 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:34 +0100 Message-Id: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi, this patchset converts the RISC-V decoder to decodetree in four major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-16]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 17-19]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 20-30]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested by Richard. [Patch 31-35] full tree available at https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5 Cheers, Bastian v4 -> v5: - fixed rebase error - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check - removed extra sign extension of sraiw - removed rs2 == 0 special cases in sraw/srlw Bastian Koppelmann (35): target/riscv: Move CPURISCVState pointer to DisasContext target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Rename trans_arith to gen_arith target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv: Convert @cs_2 insns to share translation functions target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 target/riscv: Remaining rvc insn reuse 32 bit translators target/riscv/Makefile.objs | 22 + target/riscv/insn16-32.decode | 31 + target/riscv/insn16-64.decode | 33 + target/riscv/insn16.decode | 114 ++ target/riscv/insn32-64.decode | 72 + target/riscv/insn32.decode | 203 ++ .../riscv/insn_trans/trans_privileged.inc.c | 110 + target/riscv/insn_trans/trans_rva.inc.c | 207 ++ target/riscv/insn_trans/trans_rvc.inc.c | 149 ++ target/riscv/insn_trans/trans_rvd.inc.c | 388 ++++ target/riscv/insn_trans/trans_rvf.inc.c | 388 ++++ target/riscv/insn_trans/trans_rvi.inc.c | 568 ++++++ target/riscv/insn_trans/trans_rvm.inc.c | 107 + target/riscv/translate.c | 1781 ++--------------- 14 files changed, 2611 insertions(+), 1562 deletions(-) create mode 100644 target/riscv/insn16-32.decode create mode 100644 target/riscv/insn16-64.decode create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32-64.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c Tested-by: Alistair Francis