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PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600110)(711020)(4605077)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:DM6PR01MB5067; x-ms-traffictypediagnostic: DM6PR01MB5067: x-microsoft-antispam-prvs: x-forefront-prvs: 0926B0E013 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(366004)(189003)(199004)(102836004)(186003)(6486002)(105586002)(966005)(498600001)(71200400001)(71190400001)(106356001)(110136005)(6512007)(6306002)(54906003)(3846002)(6116002)(97736004)(256004)(86362001)(52116002)(26005)(6436002)(386003)(99286004)(2501003)(6506007)(8676002)(4744005)(81166006)(81156014)(8936002)(50226002)(68736007)(7736002)(2906002)(305945005)(53936002)(14454004)(25786009)(1076003)(107886003)(39060400002)(66066001)(4326008)(486006)(476003)(2616005); DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB5067; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:3; A:3; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: z1nitpzfTlsdMWSz4G1QCurZ/CKWwK2Gq43gMe0gban5+xW+0MYIt7xkRZaXqtikRqVSWmBouzpYm/djLce1XvgARSXDwLXW5OlQN0ZvQb6SG9g41X2gNWn1zmfeUpG/qu9D7lbkN7h8dRLjYQ/j+NupfwOvrTK+lRLbGdeZk+WL2pocd9LiZoalyCKiitJuVBITN9fUMYYPWx6vl67f1Rvm4hVYSxBMxBAGO8HxwJG6lsGw0bg91Kjisl8ocoPjAXDApLj9wPkw6Rc4yNlSDxz9RhsoIuRmF8gHNAyui65hgeSle8ApNCLB0mK1GqxZsIAab2ZRu+FxCPGpGgGcrMobE060sFw0pJW48xf2moi+NWK+34UctKbll/ED+VHXqpnhInAZYPLQDAiPiAGjIpHRLWAbsngN7ABamYuy/Mg= MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f496e97-f1df-489a-1e36-08d6817a4a81 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Jan 2019 21:32:34.6076 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB5067 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe4d::71f Subject: [Qemu-devel] [PATCH v11 0/2] More fully implement ARM PMUv3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay OS , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Most of this patchset to implement the PMU has been merged already, but the interrupt-on-overflow behavior had some additional review comments. In addition to improving the overflow detection and bit-clearing logic, I split the previous patch [1] into two to (hopefully) make it more digestable. There is also a separate bugfix for one of the the already-merged patches which I already sent out separately as "target/arm: Don't clear supported PMU events when initializing PMCEID1" [2]. [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02242.html [2] - https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg05996.html Aaron Lindsay (2): target/arm: Send interrupts on PMU counter overflow target/arm: Add a timer to predict PMU counter overflow target/arm/cpu.c | 12 ++++ target/arm/cpu.h | 10 ++++ target/arm/helper.c | 133 ++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 143 insertions(+), 12 deletions(-)