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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 28 Jan 2019 09:46:39 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0S9kdfP62718022 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Jan 2019 09:46:39 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E097211C058; Mon, 28 Jan 2019 09:46:38 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA47A11C052; Mon, 28 Jan 2019 09:46:38 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 28 Jan 2019 09:46:38 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-15-166.uk.ibm.com [9.145.15.166]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 3933A2201E5; Mon, 28 Jan 2019 10:46:37 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Mon, 28 Jan 2019 10:46:06 +0100 X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19012809-0012-0000-0000-000002EDDCE4 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012809-0013-0000-0000-000021251A4A Message-Id: <20190128094625.4428-1-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-28_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=824 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901280080 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x0S9hnfM002645 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 00/19] ppc: support for the baremetal XIVE interrupt controller (POWER9) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hello, Here is a series adding support for the XIVE interrupt controller as found on POWER9 PowerNV mchines. It includes models for the baremetal IC itself and a set of fixes and extensions of the POWER9 core provided by Ben. Thanks, C. Changes in v1 (since PnvXive was last sent) : - made more use of the register values instead of caching them under PnvXive - generalized the VST accessors. - reworked indirect accesses to the TIMA with a custom get_tctx() method - fixed the translation table definitions - XiveSource and XiveENDSource objects are now sized to the maximum allowed by HW and the memory regions exposing the ESB pages are resized at runtime when the firmware configures the controller. - included changes from Ben on the POWER9 core model to fix power management instructions, add support for sreset and the HV interrupt line Benjamin Herrenschmidt (14): target/ppc: Remove some #if 0'ed code target/ppc: Make special ORs match x86 pause and don't generate on mttcg target/ppc: Fix nip on power management instructions target/ppc: Don't clobber MSR:EE on PM instructions target/ppc: Fix support for "STOP light" states on POWER9 target/ppc: Move "wakeup reset" code to a separate function target/ppc: Disable ISA 2.06 PM instructions on POWER9 target/ppc: Rename "in_pm_state" to "resume_as_sreset" target/ppc: Add POWER9 exception model target/ppc: Detect erroneous condition in interrupt delivery target/ppc: Add Hypervisor Virtualization Interrupt on POWER9 target/ppc: Add POWER9 external interrupt model ppc/xive: Make XIVE generate the proper interrupt types target/ppc: Add support for LPCR:HEIC on POWER9 Cédric Le Goater (5): ppc/xive: hardwire the Physical CAM line of the thread context ppc: externalize ppc_get_vcpu_by_pir() xive: extend the XiveRouter get_tctx() method with the page offset ppc/pnv: xive: export the TIMA memory accessors ppc/pnv: add XIVE support hw/intc/pnv_xive_regs.h | 315 ++++++ include/hw/ppc/pnv.h | 21 + include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/pnv_xive.h | 95 ++ include/hw/ppc/pnv_xscom.h | 3 + include/hw/ppc/ppc.h | 3 + include/hw/ppc/xive.h | 12 +- target/ppc/cpu-qom.h | 5 + target/ppc/cpu.h | 26 +- hw/intc/pnv_xive.c | 1698 +++++++++++++++++++++++++++++++ hw/intc/spapr_xive.c | 3 +- hw/intc/xics.c | 1 + hw/intc/xive.c | 167 ++- hw/ppc/pnv.c | 84 +- hw/ppc/pnv_core.c | 16 +- hw/ppc/ppc.c | 32 +- target/ppc/excp_helper.c | 176 ++-- target/ppc/mmu_helper.c | 12 - target/ppc/translate.c | 34 +- target/ppc/translate_init.inc.c | 36 +- hw/intc/Makefile.objs | 2 +- 21 files changed, 2593 insertions(+), 149 deletions(-) create mode 100644 hw/intc/pnv_xive_regs.h create mode 100644 include/hw/ppc/pnv_xive.h create mode 100644 hw/intc/pnv_xive.c