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[69.14.184.20]) by smtp.gmail.com with ESMTPSA id p20sm1575524ioj.63.2019.05.24.19.20.24 (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 24 May 2019 19:20:25 -0700 (PDT) From: John Arbuckle To: richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.orgd, david@gibson.dropbear.id.au, mark.cave-ayland@ilande.co.uk Date: Fri, 24 May 2019 22:20:06 -0400 Message-Id: <20190525022008.24788-1-programmingkidx@gmail.com> X-Mailer: git-send-email 2.14.3 (Apple Git-98) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP In IEEE 754 math, the arithmetic, rounding, and conversion instructions produce an intermediate result that can be regarded as having infinite precision and unbounded exponent range. When the final result has its fraction part incremented is when the Fraction Rounded bit is set. This patch implements the PowerPC FPSCR flag Fraction Rounded. Note: there are still functions in softfloat that need to be adjusted so that float_flag_rounded is fully supported. These include round_to_int(), and all legacy roundAndPack* functions. So basically anywhere that sets the float_flag_inexact. John Arbuckle (2): Implement Floating Point flag Fraction Rounded Implement the PowerPC Floating Point Status and Control Register Fraction Rounded bit fpu/softfloat.c | 15 ++++++++++++--- include/fpu/softfloat-types.h | 1 + target/ppc/fpu_helper.c | 4 ++++ 3 files changed, 17 insertions(+), 3 deletions(-)