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[67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:02 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:40 -0400 Message-Id: <20190619050447.22201-1-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU RFC PATCH v1 0/7] Support for generating x86 SSE/SSE2 test images X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi all, this is v1 of my changes to risugen in order to support generating x86 test images. It's still work-in-progress (thus marked RFC; notably, there is no support for AVX yet), but I would like to get this out there to get some early feedback on my approach. Initially, I thought adding support for arbitrarily-long instructions would be more or less enough for x86, but unfortunately this turned out not to be the case; the length variation introduced by ModR/M, SIB and displacement fields would force us to have to have at least 6 config file entries per almost every instruction, which is pretty much unmaintainable. Instead, I drew inspiration from the "memory" blocks in arm.risu for specifying memory constraints, and introduced "emit" blocks for x86. Example x86 config file with SSE and SSE2 instructions can be found in the last two commits, let me know what you think. There are still some limitations -- besides missing (E)VEX support, some forms of ModR/M are also not supported (mostly because it's hard or impossible to figure out and use the correct memory address), and the LDMXCSR instruction is currently commented out because there's no way to specify constraints on memory contents. However, this patch series should have enough code to demonstrate my intended general approach, and that's what I am looking for feedback for. Best, -Jan Jan Bobek (7): risugen_common: add insnv, randint_constr, rand_fill risugen_x86_asm: add module risugen_x86_emit: add module risugen_x86: add module risugen: allow all byte-aligned instructions x86.risu: add SSE instructions x86.risu: add SSE2 instructions risugen | 15 +- risugen_common.pm | 101 +++++++++- risugen_x86.pm | 455 ++++++++++++++++++++++++++++++++++++++++++++ risugen_x86_asm.pm | 186 ++++++++++++++++++ risugen_x86_emit.pm | 85 +++++++++ x86.risu | 245 ++++++++++++++++++++++++ 6 files changed, 1075 insertions(+), 12 deletions(-) create mode 100644 risugen_x86.pm create mode 100644 risugen_x86_asm.pm create mode 100644 risugen_x86_emit.pm create mode 100644 x86.risu