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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 0/2] Add Aspeed GPIO controller model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, andrew@aj.id.au, qemu-devel@nongnu.org, clg@kaod.org, Rashmica Gupta , joel@jms.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Rebased on Peter's target-arm.next branch. v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to read/write to minimise confusion with a 'set' of registers. Rashmica Gupta (2): hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 aspeed: add a GPIO controller to the SoC hw/arm/aspeed_soc.c | 17 + hw/gpio/Makefile.objs | 1 + hw/gpio/aspeed_gpio.c | 891 ++++++++++++++++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 3 + include/hw/gpio/aspeed_gpio.h | 92 ++++ 5 files changed, 1004 insertions(+) create mode 100644 hw/gpio/aspeed_gpio.c create mode 100644 include/hw/gpio/aspeed_gpio.h