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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 0/3] Add Aspeed GPIO controller model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@aj.id.au, qemu-devel@nongnu.org, aik@ozlabs.ru, joel@jms.id.au, Rashmica Gupta , clg@kaod.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP v5: - integrated AspeedGPIOController fields into AspeedGPIOClass - separated ast2600_3_6v and ast2600_1_8v into two classes v4: - proper interupt handling thanks to Andrew - switch statements for reading and writing suggested by Peter - some small cleanups suggested by Alexey v3: - didn't have each gpio set up as an irq - now can't access set AC on ast2400 (only exists on ast2500) - added ast2600 implementation (patch 3) - renamed a couple of variables for clarity v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to read/write to minimise confusion with a 'set' of registers. Rashmica Gupta (3): hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 aspeed: add a GPIO controller to the SoC hw/gpio: Add in AST2600 specific implementation include/hw/arm/aspeed_soc.h | 3 + include/hw/gpio/aspeed_gpio.h | 100 ++++ hw/arm/aspeed_soc.c | 17 + hw/gpio/aspeed_gpio.c | 1006 +++++++++++++++++++++++++++++++++ hw/gpio/Makefile.objs | 1 + 5 files changed, 1127 insertions(+) create mode 100644 include/hw/gpio/aspeed_gpio.h create mode 100644 hw/gpio/aspeed_gpio.c