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[83.52.55.162]) by smtp.gmail.com with ESMTPSA id w20sm22396778wmk.34.2020.02.03.00.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 00:26:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 0/6] hw/arm/raspi: Dynamically create machines based on the board revision Date: Mon, 3 Feb 2020 09:26:13 +0100 Message-Id: <20200203082619.7426-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, These patches simplify adding the raspi0/raspi1/raspi4 boards. I still need some time to figure out what is the best way to organize the SoC code because since these socs use different ARM cores, the interrupt controller are different too. Igor has been working in his "refactor main RAM allocation to use hostmem backend" series, and now v4 [1] is almost reviewed. His raspi patch [2] clashes with my work, Since it is easier for him to apply his on top of mine, I am sending these patches first. Please review, Phil. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg675738.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg675752.html Philippe Mathieu-Daudé (6): hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels hw/arm/raspi: Get board version from board revision code hw/arm/raspi: Get the SoC type name from the revision code hw/arm/raspi: Get board RAM size from board revision code hw/arm/raspi: Dynamically create machines based on the board revision hw/arm/raspi: Get the CPU core count from the revision code hw/arm/raspi.c | 178 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 135 insertions(+), 43 deletions(-)