mbox series

[v12,00/61] target/riscv: support vector extension v0.7.1

Message ID 20200701152549.1218-1-zhiwei_liu@c-sky.com (mailing list archive)
Headers show
Series target/riscv: support vector extension v0.7.1 | expand

Message

LIU Zhiwei July 1, 2020, 3:24 p.m. UTC 
This patchset implements the vector extension for RISC-V on QEMU.

You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v12).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.

You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.

Features:
  * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
  * support basic vector extension.
  * support Zvlsseg.
  * support Zvamo.
  * not support Zvediv as it is changing.
  * SLEN always equals VLEN.
  * element width support 8bit, 16bit, 32bit, 64bit.

Changelog:

v12
  * fix compile error on big endian machines.

v11
  * fix all non-ASCII characters.

v10
  * rebase to https://github.com/alistair23/qemu/tree/riscv-to-apply.next.
  * fix compile error in patch 57/61.
  * fix review tag typo.

v9
  * always set dynamic rounding mode for vector float insns.
  * bug fix atomic implementation.
  * bug fix first-only-fault.
  * some small tidy up.

v8
  * support different float rounding modes for vector instructions.
  * use lastest released TCG GVEC DUP IR.
  * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.

v7
  * move vl == 0 check to translation time by add a global cpu_vl.
  * implement vector element inline load and store function by TCG IR.
  * based on vec_element_load(store), implement some permutation instructions.
  * implement rsubs GVEC IR.
  * fixup vsmul, vmfne, vfmerge, vslidedown.
  * some other small bugs and indentation errors.

v6
  * use gvec_dup Gvec IR to accellerate move and merge.
  * a better way to implement fixed point instructions.
  * a global check when vl == 0.
  * limit some macros to only one inline function call.
  * fixup sew error when use Gvec IR.
  * fixup bugs for corner cases.

v5
  * fixup a bug in tb flags.

v4
  * no change

v3
  * move check code from execution-time to translation-time
  * use a continous memory block for vector register description.
  * vector registers as direct fields in RISCVCPUState.
  * support VLEN configure from qemu command line.
  * support ELEN configure from qemu command line.
  * support vector specification version configure from qemu command line.
  * probe pages before real load or store access.
  * use probe_page_check for no-fault operations in linux user mode.
  * generation atomic exit exception when in parallel environment.
  * fixup a lot of concrete bugs.

V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property


LIU Zhiwei (61):
  target/riscv: add vector extension field in CPURISCVState
  target/riscv: implementation-defined constant parameters
  target/riscv: support vector extension csr
  target/riscv: add vector configure instruction
  target/riscv: add an internals.h header
  target/riscv: add vector stride load and store instructions
  target/riscv: add vector index load and store instructions
  target/riscv: add fault-only-first unit stride load
  target/riscv: add vector amo operations
  target/riscv: vector single-width integer add and subtract
  target/riscv: vector widening integer add and subtract
  target/riscv: vector integer add-with-carry / subtract-with-borrow
    instructions
  target/riscv: vector bitwise logical instructions
  target/riscv: vector single-width bit shift instructions
  target/riscv: vector narrowing integer right shift instructions
  target/riscv: vector integer comparison instructions
  target/riscv: vector integer min/max instructions
  target/riscv: vector single-width integer multiply instructions
  target/riscv: vector integer divide instructions
  target/riscv: vector widening integer multiply instructions
  target/riscv: vector single-width integer multiply-add instructions
  target/riscv: vector widening integer multiply-add instructions
  target/riscv: vector integer merge and move instructions
  target/riscv: vector single-width saturating add and subtract
  target/riscv: vector single-width averaging add and subtract
  target/riscv: vector single-width fractional multiply with rounding
    and saturation
  target/riscv: vector widening saturating scaled multiply-add
  target/riscv: vector single-width scaling shift instructions
  target/riscv: vector narrowing fixed-point clip instructions
  target/riscv: vector single-width floating-point add/subtract
    instructions
  target/riscv: vector widening floating-point add/subtract instructions
  target/riscv: vector single-width floating-point multiply/divide
    instructions
  target/riscv: vector widening floating-point multiply
  target/riscv: vector single-width floating-point fused multiply-add
    instructions
  target/riscv: vector widening floating-point fused multiply-add
    instructions
  target/riscv: vector floating-point square-root instruction
  target/riscv: vector floating-point min/max instructions
  target/riscv: vector floating-point sign-injection instructions
  target/riscv: vector floating-point compare instructions
  target/riscv: vector floating-point classify instructions
  target/riscv: vector floating-point merge instructions
  target/riscv: vector floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert
    instructions
  target/riscv: narrowing floating-point/integer type-convert
    instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width floating-point reduction
    instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector mask-register logical instructions
  target/riscv: vector mask population count vmpopc
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: set-X-first mask bit
  target/riscv: vector iota instruction
  target/riscv: vector element index instruction
  target/riscv: integer extract instruction
  target/riscv: integer scalar move instruction
  target/riscv: floating-point scalar move instructions
  target/riscv: vector slide instructions
  target/riscv: vector register gather instruction
  target/riscv: vector compress instruction
  target/riscv: configure and turn on vector extension from command line

 target/riscv/Makefile.objs              |    2 +-
 target/riscv/cpu.c                      |   50 +
 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/fpu_helper.c               |   33 +-
 target/riscv/helper.h                   | 1069 +++++
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++
 target/riscv/internals.h                |   41 +
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++
 13 files changed, 9520 insertions(+), 44 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/vector_helper.c

Comments

no-reply@patchew.org July 1, 2020, 7:38 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20200701152549.1218-1-zhiwei_liu@c-sky.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1
Type: series
Message-id: 20200701152549.1218-1-zhiwei_liu@c-sky.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200626104419.15504-1-pbonzini@redhat.com -> patchew/20200626104419.15504-1-pbonzini@redhat.com
 * [new tag]         patchew/20200701152549.1218-1-zhiwei_liu@c-sky.com -> patchew/20200701152549.1218-1-zhiwei_liu@c-sky.com
Switched to a new branch 'test'
431919b target/riscv: configure and turn on vector extension from command line
0e35d15 target/riscv: vector compress instruction
6be622b target/riscv: vector register gather instruction
b9779c8 target/riscv: vector slide instructions
6a0b312 target/riscv: floating-point scalar move instructions
d91398e target/riscv: integer scalar move instruction
5fa31d1 target/riscv: integer extract instruction
7e8b41e target/riscv: vector element index instruction
97b52ff target/riscv: vector iota instruction
7aa4709 target/riscv: set-X-first mask bit
e7a21a1 target/riscv: vmfirst find-first-set mask bit
4aaf979 target/riscv: vector mask population count vmpopc
9096e02 target/riscv: vector mask-register logical instructions
3c204ad target/riscv: vector widening floating-point reduction instructions
406af0e target/riscv: vector single-width floating-point reduction instructions
cbf5ed6 target/riscv: vector wideing integer reduction instructions
9e3b9a7 target/riscv: vector single-width integer reduction instructions
f0e515c target/riscv: narrowing floating-point/integer type-convert instructions
8d7d672 target/riscv: widening floating-point/integer type-convert instructions
60e2880 target/riscv: vector floating-point/integer type-convert instructions
58f2df3 target/riscv: vector floating-point merge instructions
5ba22de target/riscv: vector floating-point classify instructions
beb2569 target/riscv: vector floating-point compare instructions
2fb6943 target/riscv: vector floating-point sign-injection instructions
db252a1 target/riscv: vector floating-point min/max instructions
2c81552 target/riscv: vector floating-point square-root instruction
fe99515 target/riscv: vector widening floating-point fused multiply-add instructions
a0a573f target/riscv: vector single-width floating-point fused multiply-add instructions
5d77f38 target/riscv: vector widening floating-point multiply
69f13ff target/riscv: vector single-width floating-point multiply/divide instructions
58dced0 target/riscv: vector widening floating-point add/subtract instructions
9138276 target/riscv: vector single-width floating-point add/subtract instructions
7c11a84 target/riscv: vector narrowing fixed-point clip instructions
36e77fe target/riscv: vector single-width scaling shift instructions
20df1e8 target/riscv: vector widening saturating scaled multiply-add
ad56fce target/riscv: vector single-width fractional multiply with rounding and saturation
5b7c118 target/riscv: vector single-width averaging add and subtract
c4e27ab target/riscv: vector single-width saturating add and subtract
df1e815 target/riscv: vector integer merge and move instructions
d9bb4dc target/riscv: vector widening integer multiply-add instructions
27c8027 target/riscv: vector single-width integer multiply-add instructions
2390fd7 target/riscv: vector widening integer multiply instructions
340fd96 target/riscv: vector integer divide instructions
a13adf3 target/riscv: vector single-width integer multiply instructions
fe02626 target/riscv: vector integer min/max instructions
80b43d4 target/riscv: vector integer comparison instructions
bf7783a target/riscv: vector narrowing integer right shift instructions
c26f462 target/riscv: vector single-width bit shift instructions
b82cf9d target/riscv: vector bitwise logical instructions
a8fad7e target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
176c4b1 target/riscv: vector widening integer add and subtract
e9ae85d target/riscv: vector single-width integer add and subtract
e44fb13 target/riscv: add vector amo operations
cd3d6cf target/riscv: add fault-only-first unit stride load
2a93e9f target/riscv: add vector index load and store instructions
85edb50 target/riscv: add vector stride load and store instructions
0b3e234 target/riscv: add an internals.h header
441a043 target/riscv: add vector configure instruction
66c80a1 target/riscv: support vector extension csr
ba5f712 target/riscv: implementation-defined constant parameters
a4675d3 target/riscv: add vector extension field in CPURISCVState

=== OUTPUT BEGIN ===
1/61 Checking commit a4675d3ad95d (target/riscv: add vector extension field in CPURISCVState)
2/61 Checking commit ba5f712b8e5f (target/riscv: implementation-defined constant parameters)
3/61 Checking commit 66c80a172784 (target/riscv: support vector extension csr)
4/61 Checking commit 441a04326ecb (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#161: 
new file mode 100644

total: 0 errors, 1 warnings, 295 lines checked

Patch 4/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/61 Checking commit 0b3e234830b7 (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 5/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/61 Checking commit 85edb50d0d03 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#274: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 6/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/61 Checking commit 2a93e9f896c8 (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#251: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#252: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 7/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

8/61 Checking commit cd3d6cf5b40a (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#161: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#162: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 227 lines checked

Patch 8/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/61 Checking commit e44fb1345c9e (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#365: FILE: target/riscv/vector_helper.c:770:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#366: FILE: target/riscv/vector_helper.c:771:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 9/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/61 Checking commit e9ae85dd393a (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#490: FILE: target/riscv/vector_helper.c:941:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 10/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/61 Checking commit 176c4b1eaa7e (target/riscv: vector widening integer add and subtract)
12/61 Checking commit a8fad7e86330 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/61 Checking commit b82cf9dd1849 (target/riscv: vector bitwise logical instructions)
14/61 Checking commit c26f462ce23e (target/riscv: vector single-width bit shift instructions)
15/61 Checking commit bf7783ac3132 (target/riscv: vector narrowing integer right shift instructions)
16/61 Checking commit 80b43d4a8a1b (target/riscv: vector integer comparison instructions)
17/61 Checking commit fe026264c936 (target/riscv: vector integer min/max instructions)
18/61 Checking commit a13adf359c2d (target/riscv: vector single-width integer multiply instructions)
19/61 Checking commit 340fd96eab6c (target/riscv: vector integer divide instructions)
20/61 Checking commit 2390fd74b02a (target/riscv: vector widening integer multiply instructions)
21/61 Checking commit 27c802719d18 (target/riscv: vector single-width integer multiply-add instructions)
22/61 Checking commit d9bb4dce4f1b (target/riscv: vector widening integer multiply-add instructions)
23/61 Checking commit df1e815b02ea (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 246 lines checked

Patch 23/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

24/61 Checking commit c4e27abf7457 (target/riscv: vector single-width saturating add and subtract)
25/61 Checking commit 5b7c118d0ebe (target/riscv: vector single-width averaging add and subtract)
26/61 Checking commit ad56fcebdb31 (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/61 Checking commit 20df1e8b388c (target/riscv: vector widening saturating scaled multiply-add)
28/61 Checking commit 36e77fefdf7c (target/riscv: vector single-width scaling shift instructions)
29/61 Checking commit 7c11a84ee6cb (target/riscv: vector narrowing fixed-point clip instructions)
30/61 Checking commit 91382760cf61 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#283: FILE: target/riscv/vector_helper.c:3260:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 271 lines checked

Patch 30/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/61 Checking commit 58dced01b6d9 (target/riscv: vector widening floating-point add/subtract instructions)
32/61 Checking commit 69f13ff746d7 (target/riscv: vector single-width floating-point multiply/divide instructions)
33/61 Checking commit 5d77f38a6bec (target/riscv: vector widening floating-point multiply)
34/61 Checking commit a0a573f5ae2e (target/riscv: vector single-width floating-point fused multiply-add instructions)
35/61 Checking commit fe99515477c2 (target/riscv: vector widening floating-point fused multiply-add instructions)
36/61 Checking commit 2c81552b08db (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#67: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2099:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#77: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2109:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 36/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

37/61 Checking commit db252a15d2c3 (target/riscv: vector floating-point min/max instructions)
38/61 Checking commit 2fb6943a452f (target/riscv: vector floating-point sign-injection instructions)
39/61 Checking commit beb2569e2f93 (target/riscv: vector floating-point compare instructions)
40/61 Checking commit 5ba22de005d7 (target/riscv: vector floating-point classify instructions)
41/61 Checking commit 58f2df31aa63 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#49: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2191:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 41/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

42/61 Checking commit 60e2880d3fad (target/riscv: vector floating-point/integer type-convert instructions)
43/61 Checking commit 8d7d67288a24 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2238:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2250:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 121 lines checked

Patch 43/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

44/61 Checking commit f0e515c9e76f (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2286:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2298:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 118 lines checked

Patch 44/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

45/61 Checking commit 9e3b9a70b596 (target/riscv: vector single-width integer reduction instructions)
46/61 Checking commit cbf5ed6c6a78 (target/riscv: vector wideing integer reduction instructions)
47/61 Checking commit 406af0e67763 (target/riscv: vector single-width floating-point reduction instructions)
48/61 Checking commit 3c204ad1ccc8 (target/riscv: vector widening floating-point reduction instructions)
49/61 Checking commit 9096e021b3f9 (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2364:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 49/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

50/61 Checking commit 4aaf97972a3c (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2394:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 50/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/61 Checking commit e7a21a1b48bc (target/riscv: vmfirst find-first-set mask bit)
52/61 Checking commit 7aa4709714ea (target/riscv: set-X-first mask bit)
53/61 Checking commit 97b52ffd5130 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2486:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 53/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

54/61 Checking commit 7e8b41e869d0 (target/riscv: vector element index instruction)
55/61 Checking commit 5fa31d1114ca (target/riscv: integer extract instruction)
56/61 Checking commit d91398e0eea0 (target/riscv: integer scalar move instruction)
57/61 Checking commit 6a0b31281821 (target/riscv: floating-point scalar move instructions)
58/61 Checking commit b9779c8ffa7f (target/riscv: vector slide instructions)
59/61 Checking commit 6be622b771ae (target/riscv: vector register gather instruction)
60/61 Checking commit 0e35d1545a32 (target/riscv: vector compress instruction)
61/61 Checking commit 431919b50662 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200701152549.1218-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Alistair Francis July 2, 2020, 3:32 a.m. UTC | #2 
On Wed, Jul 1, 2020 at 8:26 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> This patchset implements the vector extension for RISC-V on QEMU.
>
> You can also find the patchset and all *test cases* in
> my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v12).
> All the test cases are in the directory qemu/tests/riscv/vector/. They are
> riscv64 linux user mode programs.
>
> You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.
>
> Features:
>   * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
>   * support basic vector extension.
>   * support Zvlsseg.
>   * support Zvamo.
>   * not support Zvediv as it is changing.
>   * SLEN always equals VLEN.
>   * element width support 8bit, 16bit, 32bit, 64bit.
>
> Changelog:
>
> v12
>   * fix compile error on big endian machines.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> v11
>   * fix all non-ASCII characters.
>
> v10
>   * rebase to https://github.com/alistair23/qemu/tree/riscv-to-apply.next.
>   * fix compile error in patch 57/61.
>   * fix review tag typo.
>
> v9
>   * always set dynamic rounding mode for vector float insns.
>   * bug fix atomic implementation.
>   * bug fix first-only-fault.
>   * some small tidy up.
>
> v8
>   * support different float rounding modes for vector instructions.
>   * use lastest released TCG GVEC DUP IR.
>   * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.
>
> v7
>   * move vl == 0 check to translation time by add a global cpu_vl.
>   * implement vector element inline load and store function by TCG IR.
>   * based on vec_element_load(store), implement some permutation instructions.
>   * implement rsubs GVEC IR.
>   * fixup vsmul, vmfne, vfmerge, vslidedown.
>   * some other small bugs and indentation errors.
>
> v6
>   * use gvec_dup Gvec IR to accellerate move and merge.
>   * a better way to implement fixed point instructions.
>   * a global check when vl == 0.
>   * limit some macros to only one inline function call.
>   * fixup sew error when use Gvec IR.
>   * fixup bugs for corner cases.
>
> v5
>   * fixup a bug in tb flags.
>
> v4
>   * no change
>
> v3
>   * move check code from execution-time to translation-time
>   * use a continous memory block for vector register description.
>   * vector registers as direct fields in RISCVCPUState.
>   * support VLEN configure from qemu command line.
>   * support ELEN configure from qemu command line.
>   * support vector specification version configure from qemu command line.
>   * probe pages before real load or store access.
>   * use probe_page_check for no-fault operations in linux user mode.
>   * generation atomic exit exception when in parallel environment.
>   * fixup a lot of concrete bugs.
>
> V2
>   * use float16_compare{_quiet}
>   * only use GETPC() in outer most helper
>   * add ctx.ext_v Property
>
>
> LIU Zhiwei (61):
>   target/riscv: add vector extension field in CPURISCVState
>   target/riscv: implementation-defined constant parameters
>   target/riscv: support vector extension csr
>   target/riscv: add vector configure instruction
>   target/riscv: add an internals.h header
>   target/riscv: add vector stride load and store instructions
>   target/riscv: add vector index load and store instructions
>   target/riscv: add fault-only-first unit stride load
>   target/riscv: add vector amo operations
>   target/riscv: vector single-width integer add and subtract
>   target/riscv: vector widening integer add and subtract
>   target/riscv: vector integer add-with-carry / subtract-with-borrow
>     instructions
>   target/riscv: vector bitwise logical instructions
>   target/riscv: vector single-width bit shift instructions
>   target/riscv: vector narrowing integer right shift instructions
>   target/riscv: vector integer comparison instructions
>   target/riscv: vector integer min/max instructions
>   target/riscv: vector single-width integer multiply instructions
>   target/riscv: vector integer divide instructions
>   target/riscv: vector widening integer multiply instructions
>   target/riscv: vector single-width integer multiply-add instructions
>   target/riscv: vector widening integer multiply-add instructions
>   target/riscv: vector integer merge and move instructions
>   target/riscv: vector single-width saturating add and subtract
>   target/riscv: vector single-width averaging add and subtract
>   target/riscv: vector single-width fractional multiply with rounding
>     and saturation
>   target/riscv: vector widening saturating scaled multiply-add
>   target/riscv: vector single-width scaling shift instructions
>   target/riscv: vector narrowing fixed-point clip instructions
>   target/riscv: vector single-width floating-point add/subtract
>     instructions
>   target/riscv: vector widening floating-point add/subtract instructions
>   target/riscv: vector single-width floating-point multiply/divide
>     instructions
>   target/riscv: vector widening floating-point multiply
>   target/riscv: vector single-width floating-point fused multiply-add
>     instructions
>   target/riscv: vector widening floating-point fused multiply-add
>     instructions
>   target/riscv: vector floating-point square-root instruction
>   target/riscv: vector floating-point min/max instructions
>   target/riscv: vector floating-point sign-injection instructions
>   target/riscv: vector floating-point compare instructions
>   target/riscv: vector floating-point classify instructions
>   target/riscv: vector floating-point merge instructions
>   target/riscv: vector floating-point/integer type-convert instructions
>   target/riscv: widening floating-point/integer type-convert
>     instructions
>   target/riscv: narrowing floating-point/integer type-convert
>     instructions
>   target/riscv: vector single-width integer reduction instructions
>   target/riscv: vector wideing integer reduction instructions
>   target/riscv: vector single-width floating-point reduction
>     instructions
>   target/riscv: vector widening floating-point reduction instructions
>   target/riscv: vector mask-register logical instructions
>   target/riscv: vector mask population count vmpopc
>   target/riscv: vmfirst find-first-set mask bit
>   target/riscv: set-X-first mask bit
>   target/riscv: vector iota instruction
>   target/riscv: vector element index instruction
>   target/riscv: integer extract instruction
>   target/riscv: integer scalar move instruction
>   target/riscv: floating-point scalar move instructions
>   target/riscv: vector slide instructions
>   target/riscv: vector register gather instruction
>   target/riscv: vector compress instruction
>   target/riscv: configure and turn on vector extension from command line
>
>  target/riscv/Makefile.objs              |    2 +-
>  target/riscv/cpu.c                      |   50 +
>  target/riscv/cpu.h                      |   82 +-
>  target/riscv/cpu_bits.h                 |   15 +
>  target/riscv/csr.c                      |   75 +-
>  target/riscv/fpu_helper.c               |   33 +-
>  target/riscv/helper.h                   | 1069 +++++
>  target/riscv/insn32-64.decode           |   11 +
>  target/riscv/insn32.decode              |  372 ++
>  target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++
>  target/riscv/internals.h                |   41 +
>  target/riscv/translate.c                |   27 +-
>  target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++
>  13 files changed, 9520 insertions(+), 44 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
>  create mode 100644 target/riscv/internals.h
>  create mode 100644 target/riscv/vector_helper.c
>
> --
> 2.23.0
>
>