[V4,0/6] Support RISC-V migration

Message

Yifei Jiang Oct. 26, 2020, 11:55 a.m. UTC

This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.

A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.

changes since v3
1. Apply Alistair's patch to exend get/set_field():
   https://www.mail-archive.com/[e-mail]/msg753575.html
2. Remake the patch: Merge m/vsstatus and m/vsstatush into one uint64_t
   unit.

Changes since v2:
1. Move vmstate_riscv_cpu declaration to internals.h.
2. Merge m/vsstatus and m/vsstatush into one uint64_t unit.

Changes since v1:
1. Add license head to target/riscv/machine.c.
2. Regenerate some state of PMP at post_load hook.

Yifei Jiang (6):
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
  target/riscv: Add basic vmstate description of CPU
  target/riscv: Add PMP state description
  target/riscv: Add H extension state description
  target/riscv: Add V extension state description
  target/riscv: Add sifive_plic vmstate

 hw/intc/sifive_plic.c     |  26 ++++-
 hw/intc/sifive_plic.h     |   1 +
 target/riscv/cpu.c        |  16 ++--
 target/riscv/cpu.h        |  24 +++--
 target/riscv/cpu_bits.h   |  19 +---
 target/riscv/cpu_helper.c |  35 ++-----
 target/riscv/csr.c        |  18 ++--
 target/riscv/internals.h  |   4 +
 target/riscv/machine.c    | 196 ++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build  |   3 +-
 target/riscv/op_helper.c  |  11 +--
 target/riscv/pmp.c        |  29 +++---
 target/riscv/pmp.h        |   2 +
 13 files changed, 290 insertions(+), 94 deletions(-)
 create mode 100644 target/riscv/machine.c

Comments

Alistair Francis Oct. 27, 2020, 8:26 p.m. UTC | #1

On Mon, Oct 26, 2020 at 4:58 AM Yifei Jiang <[e-mail]> wrote:
>
> This patches supported RISC-V migration based on tcg accel. And we have
> verified related migration features such as snapshot and live migration.
>
> A few weeks ago, we submitted RFC patches about supporting RISC-V migration
> based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
> And we found that tcg accelerated migration can be supported with a few
> changes. Most of the devices have already implemented the migration
> interface, so, to achieve the tcg accelerated migration, we just need to
> add vmstate of both cpu and sifive_plic.
>
> changes since v3
> 1. Apply Alistair's patch to exend get/set_field():
>    https://www.mail-archive.com/[e-mail]/msg753575.html
> 2. Remake the patch: Merge m/vsstatus and m/vsstatush into one uint64_t
>    unit.
>
> Changes since v2:
> 1. Move vmstate_riscv_cpu declaration to internals.h.
> 2. Merge m/vsstatus and m/vsstatush into one uint64_t unit.
>
> Changes since v1:
> 1. Add license head to target/riscv/machine.c.
> 2. Regenerate some state of PMP at post_load hook.
>
> Yifei Jiang (6):
>   target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
>   target/riscv: Add basic vmstate description of CPU
>   target/riscv: Add PMP state description
>   target/riscv: Add H extension state description
>   target/riscv: Add V extension state description
>   target/riscv: Add sifive_plic vmstate

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/intc/sifive_plic.c     |  26 ++++-
>  hw/intc/sifive_plic.h     |   1 +
>  target/riscv/cpu.c        |  16 ++--
>  target/riscv/cpu.h        |  24 +++--
>  target/riscv/cpu_bits.h   |  19 +---
>  target/riscv/cpu_helper.c |  35 ++-----
>  target/riscv/csr.c        |  18 ++--
>  target/riscv/internals.h  |   4 +
>  target/riscv/machine.c    | 196 ++++++++++++++++++++++++++++++++++++++
>  target/riscv/meson.build  |   3 +-
>  target/riscv/op_helper.c  |  11 +--
>  target/riscv/pmp.c        |  29 +++---
>  target/riscv/pmp.h        |   2 +
>  13 files changed, 290 insertions(+), 94 deletions(-)
>  create mode 100644 target/riscv/machine.c
>
> --
> 2.19.1
>
>