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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q16sm17429756wrn.13.2020.11.27.14.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 14:51:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 0/3] target/openrisc: Move pic_cpu code into CPU object Date: Fri, 27 Nov 2020 22:51:24 +0000 Message-Id: <20201127225127.14770-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Jia Liu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. The main aim of this patch series is to make that refactoring, which fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(), and removes one callsite of the qemu_allocate_irqs() function. Patch 1 is a minor bugfix noticed along the way; patch 2 is there to make the change in patch 3 simpler and clearer to review. Tested with 'make check' and 'make check-acceptance'. thanks -- PMM Peter Maydell (3): hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y" target/openrisc: Move pic_cpu code into CPU object proper target/openrisc/cpu.h | 1 - hw/openrisc/openrisc_sim.c | 46 +++++++++++++++++----------- hw/openrisc/pic_cpu.c | 61 -------------------------------------- target/openrisc/cpu.c | 32 ++++++++++++++++++++ hw/openrisc/Kconfig | 1 + hw/openrisc/meson.build | 2 +- 6 files changed, 63 insertions(+), 80 deletions(-) delete mode 100644 hw/openrisc/pic_cpu.c