Message ID | 20210108185154.8108-1-leif@nuviainc.com (mailing list archive) |
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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:55 -0800 (PST) From: Leif Lindholm <leif@nuviainc.com> To: qemu-devel@nongnu.org Subject: [PATCH v3 0/6] target/arm: various changes to cpu.h Date: Fri, 8 Jan 2021 18:51:48 +0000 Message-Id: <20210108185154.8108-1-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=leif@nuviainc.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> |
Series |
target/arm: various changes to cpu.h
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On Fri, 8 Jan 2021 at 18:51, Leif Lindholm <leif@nuviainc.com> wrote: > > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS). > > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined > by the ARM ARM. > > Third, add field definitions for CLIDR (excepting the Ttype<n> fields, since > I was unsure of prefererred naming - Ttype7-Ttype1?). > > Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c, > > Lastly, add all ID_ (aarch32) registers/fields. > > Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be > submitting shortly, and some of those features also exist for aarch32. Applied to target-arm.next, thanks. -- PMM