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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id k22sm4261481edv.33.2021.01.15.07.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:30:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Fri, 15 Jan 2021 16:30:40 +0100 Message-Id: <20210115153049.3353008-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, This is how I understand the ecSPI reset works, after looking at the IMX6DQRM.pdf datasheet. This is a respin of Ben's v5 series [*]. Since v6: - Dropped "Reduce 'change_mask' variable scope" patch - Fixed inverted reset logic - Added Juan R-b tags - Removed 'RFC' tag as tests pass Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com> (queued on riscv-next). Copy of Ben's v5 cover: This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is disabled - remove imx_spi_update_irq() in imx_spi_reset() - round up the tx burst length to be multiple of 8 - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect [*] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg02333.html Diff with v6: Key: [----] : patches are identical [####] : number of functional differences between upstream/downstream patch [down] : patch is downstream-only The flags [FC] indicate (F)unctional and (C)ontextual differences, respective= ly 001/9:[----] [--] 'hw/ssi: imx_spi: Use a macro for number of chip selects su= pported' 002/9:[----] [--] 'hw/ssi: imx_spi: Remove pointless variable initialization' 003/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG reg= ister value' 004/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_read() to handle block dis= abled' 005/9:[0003] [FC] 'hw/ssi: imx_spi: Rework imx_spi_write() to handle block di= sabled' 006/9:[----] [--] 'hw/ssi: imx_spi: Disable chip selects when controller is d= isabled' 007/9:[----] [--] 'hw/ssi: imx_spi: Round up the burst length to be multiple = of 8' 008/9:[----] [--] 'hw/ssi: imx_spi: Correct the burst length > 32 bit transfe= r logic' 009/9:[----] [--] 'hw/ssi: imx_spi: Correct tx and rx fifo endianness' Bin Meng (4): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daud=C3=A9 (4): hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 +- hw/ssi/imx_spi.c | 137 +++++++++++++++++++++++---------------- 2 files changed, 86 insertions(+), 56 deletions(-) --=20 2.26.2