[v2,0/1] target/arm: Fix SCR_EL3 migration issue

Message

Zhijian Li (Fujitsu)" via Feb. 3, 2021, 4:55 p.m. UTC

The SCR_EL3 register reset value (0)  and the value produced when
writing 0 via the scr_write function (set as writefn in the register
struct) differ. This causes migration to fail.

Ultimately, this is due to incorrect handling of context-dependent
behavior of the RES1 bits of SCR_EL3. The FW and AW bits should be
forced to 1 only if there is no support for AArch32 at EL1 or above.

This patch improves the scr_write RES1 bit handling and adds a reset
function which will initialize SCR_EL3 to 0x30 on AArch64-only CPUs, and
0 if AArch32 is supported at EL1 or above.

Failing invocation:
$ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic
QEMU 5.2.0 monitor - type 'help' for more information
(qemu) migrate "exec:cat > img"
(qemu) q
$ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic -incoming "exec:cat img"
qemu-system-arm: error while loading state for instance 0x0 of device 'cpu'
qemu-system-arm: load of migration failed: Operation not permitted


Mike Nawrocki (1):
  target/arm: Fix SCR RES1 handling

 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 16 ++++++++++++++--
 2 files changed, 19 insertions(+), 2 deletions(-)