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Wed, 10 Feb 2021 14:04:38 -0800 (PST) Date: Wed, 10 Feb 2021 14:04:21 -0800 Message-Id: <20210210220426.3577804-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.30.0.478.g8a0d178c01-goog Subject: [PATCH v3 0/5] hw/i2c: Add NPCM7XX SMBus Device To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3dlgkYAgKCr81zmftyxmlttlqj.htrvjrz-ij0jqstslsz.twl@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Hao Wu X-Patchwork-Original-From: Hao Wu via From: Hao Wu This patch set implements the System manager bus (SMBus) module in NPCM7XX SoC. Basically, it emulates the data transactions of the module, not the SDA/SCL levels. We have also added a QTest which contains read and write operations for both single-byte and FIFO mode, and added basic I2C devices for npcm750-evb and quanta-gsj boards. Changes since v2: - Remove first patch (GPIO) since it's already applied to target-arm.next - Rename NPCM7XX_SMBUS_FIFO_EN to NPCM7XX_SMBUS_VERSION_FIFO_SUPPORTED to indicate it's a register field of the VERSION reg. - Add select AT24C in hw/arm/Kconfig. - Minor additional commit messages and comments to clarify things. Changes since v1: - Fix errors for i2c device addresses for temperature sensors in GSJ machine - Use at24c device to emulate GSJ EEPROM. It supports more than 256 bytes. - Fill in VMState in npcm7xx_smbus.c - Change commit message in patch 3 and 4 - Fix order in npcm7xx.c IRQ list - Add a few extra comments to make things clearer Hao Wu (5): hw/i2c: Implement NPCM7XX SMBus Module Single Mode hw/arm: Add I2C sensors for NPCM750 eval board hw/arm: Add I2C sensors and EEPROM for GSJ machine hw/i2c: Add a QTest for NPCM7XX SMBus Device hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode docs/system/arm/nuvoton.rst | 2 +- hw/arm/Kconfig | 1 + hw/arm/npcm7xx.c | 68 +- hw/arm/npcm7xx_boards.c | 46 ++ hw/i2c/meson.build | 1 + hw/i2c/npcm7xx_smbus.c | 1099 ++++++++++++++++++++++++++++++ hw/i2c/trace-events | 12 + include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 113 +++ tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_smbus-test.c | 495 ++++++++++++++ 11 files changed, 1823 insertions(+), 17 deletions(-) create mode 100644 hw/i2c/npcm7xx_smbus.c create mode 100644 include/hw/i2c/npcm7xx_smbus.h create mode 100644 tests/qtest/npcm7xx_smbus-test.c