mbox series

[v2,0/3] target/arm: Add support for FEAT_SSBS

Message ID 20210216224543.16142-1-rebecca@nuviainc.com (mailing list archive)
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Series target/arm: Add support for FEAT_SSBS | expand

Message

Rebecca Cran Feb. 16, 2021, 10:45 p.m. UTC 
Add support for FEAT_SSBS, Speculative Store Bypass Safe. SSBS is an
optional feature in ARMv8.0 and is mandatory in ARMv8.5.

Changes from v1 to v2:

o Removed changes to cpsr_write_from_spsr_elx and cpsr_read_for_spsr_elx.
o Moved the SSBS case in translate-a64.c above DIT to keep the numbers in
  order.
o Moved the check for SCTLR_DSSBS_32 in take_aarch32_exception.

Rebecca Cran (3):
  target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
  target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
  target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

 target/arm/cpu.c           |  4 +++
 target/arm/cpu.h           | 15 +++++++-
 target/arm/cpu64.c         |  5 +++
 target/arm/helper.c        | 37 ++++++++++++++++++++
 target/arm/internals.h     |  6 ++++
 target/arm/translate-a64.c | 12 +++++++
 6 files changed, 78 insertions(+), 1 deletion(-)

Comments

Peter Maydell March 5, 2021, 11:22 a.m. UTC | #1 
On Tue, 16 Feb 2021 at 22:45, Rebecca Cran <rebecca@nuviainc.com> wrote:
>
>
> Add support for FEAT_SSBS, Speculative Store Bypass Safe. SSBS is an
> optional feature in ARMv8.0 and is mandatory in ARMv8.5.
>
> Changes from v1 to v2:
>
> o Removed changes to cpsr_write_from_spsr_elx and cpsr_read_for_spsr_elx.
> o Moved the SSBS case in translate-a64.c above DIT to keep the numbers in
>   order.
> o Moved the check for SCTLR_DSSBS_32 in take_aarch32_exception.
>


Applied to target-arm.next, thanks.

-- PMM